Datasheet

AD9943/AD9944
Rev. B | Page 6 of 20
TIMING SPECIFICATIONS
C
L
= 20 pF, f
SAMP
= 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
Table 5.
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
40 ns
DATACLK High/Low Pulse Width t
ADC
16 20 ns
SHP Pulse Width t
SHP
10 ns
SHD Pulse Width t
SHD
10 ns
CLPOB Pulse Width
1
t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
10 ns
SHP Rising Edge to SHD Rising Edge t
S2
16 20 ns
Internal Clock Delay t
ID
3.0 ns
DATA OUTPUTS
Output Delay t
OD
9.5 ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.