Datasheet

AD9943/AD9944
Rev. B | Page 14 of 20
SERIAL INTERFACE
t
LS
t
LH
SDATA
SCK
SL
TEST BIT
A2 0A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. ALL 12 DATA BITS D0–D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED
FOR THE UNDEFINED BITS.
4. TEST BIT IS FOR INTERNAL USE ONLY AND MUST BE SET LOW.
D11
02905-B-011
Figure 10. Serial Write Operation
SDAT
A
A0 A1 A2 D0 D1 D2 D3 D4 D5 D10 D11
SCK
SL
0
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 12-BIT DATA-WORD. (ALL 12 BITS MUST BE WRITTEN.)
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
D0 D1 D10 D11
D0
...
...
...
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2D1
...
...
1
16
234567 8910
15
1817 2827
30
29
31
TEST
BIT
02905-B-012
Figure 11. Continuous Serial Write Operation to All Registers