Datasheet

AD9940
Rev. 0 | Page 5 of 20
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = OVDD = TCVDD = HVDD = RGVDD = 2.7 V, −25°C to +85°C, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 μA
Low Level Input Current I
IL
10 μA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA V
OH
2.2 V
Low Level Output Voltage, I
OL
= 2 mA V
OL
0.5 V
CLI INPUT
High Level Input Voltage V
IH–CLI
1.85 V
Low Level Input Voltage V
IL–CLI
0.85 V
RG-DRIVER AND H-DRIVER OUTPUTS (powered by HVDD, RGVDD)
High Level Output Voltage (at max output current) V
OH
VDD − 0.5 V
Low Level Output Voltage (at max output current) V
OL
0.5 V
Maximum Output Current (programmable)
H-Driver (per output) 64 mA
RG-Driver, HL-Driver 15 mA
Maximum Load Capacitance
H-Driver (per output) 100 pF
RG-Driver, HL-Driver 50 pF
TIMING SPECIFICATIONS (SLAVE TIMING MODE)
See Figure 10 for Timing Diagram.
Table 4.
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI)
CLI Clock Period T
CLI
18 ns
CLI High Pulse Width T
ADC
9 ns
Internal Delay from CLI to First Tap T
CLIDLY
6 ns
SAMPLE CLOCKS
SHP Rising to SHD Rising T
S1
7.4 9 ns
ADCLK Edge Placement for AD9941 T
REC
3 ns
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Rising Edge to SDATA Valid Hold t
DH
10 ns