Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ANALOG SPECIFICATIONS
- DIGITAL SPECIFICATIONS
- TIMING SPECIFICATIONS (SLAVE TIMING MODE)
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- DATA BIT DESCRIPTIONS
- SERIAL INTERFACE TIMING
- SYSTEM OVERVIEW
- PRECISION TIMING, HIGH SPEED TIMING GENERATION
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD9940
Rev. 0 | Page 3 of 20
SPECIFICATIONS
Table 1.
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating −25 +85 °C
Storage −65 +150 °C
MAXIMUM CLOCK RATE 56 MHz
POWER SUPPLY VOLTAGE
AVDD, TCVDD (AFE, Timing Core) 2.7 3.0 3.6 V
OVDD (Analog Buffer) 2.7 3.0 3.6 V
DVDD (Digital) 2.7 3.0 3.6 V
HVDD (H1 to H4 Drivers) 2.7 3.0 3.6 V
RGVDD (RG Driver) 2.7 3.0 3.6 V
POWER DISSIPATION
1
56 MHz, AFE supplies = 2.7 V, HVDD = RGVDD = 3.2 V, 70 pF, H1 to H4 Loading 265 mW
56 MHz, AFE supplies = 3.0 V, HVDD = RGVDD = 3.2 V, 70 pF, H1 to H4 Loading 275 mW
56 MHz, AFE supplies = 2.7 V, no H or RG drivers 105 mW
56 MHz, AFE supplies = 3.0 V, no H or RG drivers 115 mW
Standby Mode 2 mW
1
The total power dissipated by the HVDD supply can be approximated using the following equation:
Total HVDD Power = (C
LOAD
× HVDD × Pixel Frequency) × HVDD
Reducing the H-loading and/or using a lower HVDD supply reduces the power dissipation.