Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ANALOG SPECIFICATIONS
- DIGITAL SPECIFICATIONS
- TIMING SPECIFICATIONS (SLAVE TIMING MODE)
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- DATA BIT DESCRIPTIONS
- SERIAL INTERFACE TIMING
- SYSTEM OVERVIEW
- PRECISION TIMING, HIGH SPEED TIMING GENERATION
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS
AD9940
Rev. 0 | Page 15 of 20
H2/H4
HL
CCD SIGNA
L
RG
1
4
5
6
8
PROGRAMMABLE CLOCK POSITIONS:
1
RG POLARITY.
2
RG RISING EDGE.
3
RG FALLING EDGE.
4
SHP SAMPLE LOCATION.
5
SHD SAMPLE LOCATION.
6
H1/H3 POLARITY.
7
H1/H3 RISING EDGE POSITION.
8
H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).
9
HL POLARITY.
10
HL RISING EDGE.
11
HL FALLING EDGE.
05261-008
23
H1/H3
7
9
11
10
Figure 9. High Speed Clock Programmable Locations
N N+1 N+2 N+9 N+10
t
REC
SHPLOC
SHDLOC
ADCLK
(FOR AD9941)
DIFFP
DIFFN
CCD
SIGNAL
t
S1
05261-009
VALID
Figure 10. SHP, SHD, and Data Output Timing