Datasheet

AD9923A
Rev. A | Page 72 of 84
Address
(Hex)
Data
Bits
Default
Value
Update
Type Name Description
[7:4] 1 H2DRV H2 drive strength.
[11:8] 1 H3DRV H3 drive strength.
[15:12] 1 H4DRV H4 drive strength.
[19:16] 1 HLDRV HL drive strength.
[23:20] 1 RGDRV RG drive strength.
37 [5:0] 24 SCK SHPLOC SHP sample location.
[13:8] 0 SHDLOC SHD sample location.
38 [5:0] 0 SCK DOUTPHASE DOUT (internal signal) phase control.
[7:6] 0 Unused Must be set to 0.
[8] 0 DCLKMODE DCLK mode.
0: DCLK tracks DOUT phase.
1: DCLK phase is fixed.
[10:9] 2 DOUTDELAY Data output delay (t
OD
) with respect to DCLK rising edge.
0: no delay.
1: ~4 ns.
2: ~8 ns.
3: ~12 ns.
[11] 0 DCLKINV Invert DCLK output.
0: no inversion.
1: inversion of DCLK.
Table 50. CLPOB and PBLK Masking Registers
Address
(Hex)
Data
Bits Default Value
Update
Type Name Description
40 [11:0] FFF VD CLPOBMASKSTART1 CLPOB Masking Start Line 1.
[12] 0 Unused Must be set to 0.
[24:13] FFF CLPOBMASKEND1 CLPOB Masking End Line 1.
41 [11:0] FFF VD CLPOBMASKSTART2 CLPOB Masking Start Line 2.
[12] 0 Unused Must be set to 0.
[24:13] FFF CLPOBMASKEND2 CLPOB Masking End Line 2.
42 [11:0] FFF VD CLPOBMASKSTART3 CLPOB Masking Start Line 3.
[12] 0 Unused Must be set to 0.
[24:13] FFF CLPOBMASKEND3 CLPOB Masking End Line 3.
43 [11:0] FFF VD PBLKMASKSTART1 PBLK Masking Start Line 1.
[12] 0 Unused Must be set to 0.
[24:13] FFF PBLKMASKEND1 PBLK Masking End Line 1.
44 [11:0] FFF VD PBLKMASKSTART12 PBLK Masking Start Line 2.
[12] 0 Unused Must be set to 0.
[24:13] FFF PBLKMASKEND2 PBLK Masking End Line 2.
45 [11:0] FFF VD PBLKMASKSTART3 PBLK Masking Start Line 3.
[12] 0 Unused Must be set to 0.
[24:13] FFF PBLKMASKEND3 PBLK Masking End Line 3.