Datasheet

AD9923A
Rev. A | Page 71 of 84
Table 49. Timing Core Registers
Address
(Hex)
Data
Bits
Default
Value
Update
Type Name Description
30 [0] 0 SCK CLIDIVIDE Divide CLI input frequency by 2.
0: no divide.
1: divide by 2.
31 [5:0] 0 SCK H1POSLOC H1 rising edge location.
[13:8] 20 H1NEGLOC H1 falling edge location.
[16] 1 H1H2POL H1/H2 polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
32 [5:0] 0 SCK H3POSLOC H3 rising edge location.
[13:8] 20 H3NEGLOC H3 falling edge location.
[16] 1 H3H4POL H3/H4 polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
33 [5:0] 0 SCK HLPOSLOC HL rising edge location.
[13:8] 20 HLNEGLOC HL falling edge location.
[16] 1 HLPOL HL polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
34 [5:0] 0 SCK RGPOSLOC RG rising edge location.
[13:8] 10 RGNEGLOC RG falling edge location.
[16] 1 RGPOL RG polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
35 [0] 0 VD H1H2RETIME
Retime HBLK for H1/H2 to the internal H1 clock. The preferred setting is 1,
which adds one cycle of delay to the HBLK toggle positions.
0: no retime.
1: retime.
[1] 0 H3H4RETIME Retime HBLK for H3/H4 to the internal H3 clock.
[2] 0 HLRETIME Retime HBLK for HL to the internal HL clock.
[3] 0 HLHBLKEN Enable HBLK for HL output.
0: disable.
1: enable.
[6:4] 0 HBLKWIDTH Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0: same frequency as pixel rate.
1: 1/2 pixel frequency, that is, it doubles the H1 to H4 pulse width.
2: 1/4 pixel frequency.
3: 1/6 pixel frequency.
4: 1/8 pixel frequency.
5: 1/10 pixel frequency.
6: 1/12 pixel frequency.
7: 1/14 pixel frequency.
36 [3:0] 1 SCK H1DRV H1 drive strength.
0: off.
1: 4.3 mA.
2: 8.6 mA.
3: 12.9 mA.
4: 17.2 mA.
5: 21.5 mA.
6: 25.8 mA.
7: 30.1 mA.