Datasheet

AD9923A
Rev. A | Page 70 of 84
Table 47. Miscellaneous Registers
Address
(Hex)
Data
Bits
Default
Value
Update
Type
Name Description
10 [0] 0 SCK SW_RST Software reset. Bit resets to 0.
1: reset Register 0x00 to Register 0x91 to default values.
11 [0] 0 VD OUTCONTROL 0: make all outputs dc inactive.
1: enable outputs at next VD edge.
12 [0] 1 SCK SYNCENABLE
0: configure Ball G7 as an output signal, determined by
Register 0x12, Bits[9:8].
1: external synchronization enable (configure Ball G7 as SYNC input).
[7:1] 0 TEST Test mode only. Must be set to 0.
[9:8] 0 OUTPUTPBLK When SYNCENABLE = 0, selects which signal is output on the SYNC pin.
0: CLPOB.
1: PBLK.
2: GPO (from Register 0x1A).
3: TESTOUT (from shutter registers).
13 [0] 0 SCK SYNCPOL SYNC active polarity.
0: active low.
1: active high.
14 [0] 0 SCK SYNCSUSPEND Suspends clocks during SYNC active pulse.
0: don’t suspend.
1: suspend.
15 [0] 0 SCK TGCORE_RSTB Timing core reset bar.
0: reset TG core.
1: resume operation.
16 [0] 0 SCK OSC_RST CLO oscillator reset.
0: oscillator in power-down state.
1: resume oscillator operation.
17 [7:0] 0 SCK TEST1 Test mode only. Must be set to 0.
[8] 0 TEST2 Test mode only. Must be set to 0.
18 [11:0] 0 VD UPDATE
Serial update line. Sets the HD line within the field to update the VD
updated registers.
19 [0] 0 SCK PREVENTUP Prevents the updating of the VD updated registers.
0: normal update.
1: prevent update of VD updated registers.
1A [0] 0 VD GPO
General-purpose output (GPO) value when SYNCENABLE = 0 and
OUTPUTPBLK = 2.
0: GPO is low at next VD edge.
1: GPO is high at next VD edge.
Table 48. VD/HD Registers
Address
(Hex)
Data
Bits
Default
Value
Update
Type Name Description
20 [0] 0 SCK MASTER VD/HD master or slave mode.
0: slave mode.
1: master mode.
21 [0] 0 SCK VDHDPOL VD/HD active polarity.
0: low.
1: high.
22 [12:0] 0 VD HDRISE Rising edge location for HD.
[24:13] 0 VDRISE Rising edge location for VD.