Datasheet

AD9923A
Rev. A | Page 64 of 84
05586-090
3
V1 V2 V3 V4 V6
15
6
12
0.1µF
4.7µF
6.3V
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
10V
0.1µF
25V
0.1µF
0.1µF
4.7µF
10V
4.7µF
6.3V
2.2µF
25V
CLI
SERIAL INTERFACE (FROM ASIC/DSP)
VERTICAL SYNC (TO/FROM ASIC/DSP)
HORIZONTAL SYNC (TO/FROM ASIC/DSP)
RESETB (FROM ASIC/DSP)
+3V SUPPLY
+3V SUPPLY
+3V SUPPLY
+3V SUPPLY
CLO
MASTER CLOCK INPUT
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
VSUB OUTPUT (TO CCD BIAS CIRCUIT)
STROBE CONTROL OUTPUT
MECHANICAL SHUTTER CONTROL
OUTPUT
CCDGND
H, RG
OUTPUTS
(TO CCD)
+3V ANALOG
SUPPLY
+3V H,
RG SUPPLY
+3V H,
RG SUPPLY
VLL
VL1 VL2
VMM
VM1 VM2
VH1 VH2 V5A V5B V7A V7B
V10 V11 V12 V13
VERTICAL OUTPUTS (TO CCD)
SUBCK OUTPUT (TO CCD)
SUBCK
NC = NOT INTERNALLY
CONNECTED
DCLK OUTPUT
DATA OUTPUTS
D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) DCLK RSTB HD VD SYNC SL SCK SDI VSUB STROBE MSHUT
REFB
REFT
CCDIN
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
RG
HL
H4
H3
H2
H1
CCD SIGNAL
INPUT
RGVSS
HVSS
AVDD
TCVDD
RGVDD
HVDD
AD9923ABBCZ
(Not to Scale)
VH SUPPLY
VL SUPPLY
VDD2 VDD1
VSS2 VSS1
V9 V8
DRVDD
DVDD1
DVDD2
DVDD2
DVDD2
TEST3
VDR_EN
NC
TEST1
TEST0
DRVSS
DVSS1
DVSS2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L4
E1
K8
L8
L7
J8
K11
K4
J7
J5
L5
F2
K9
A11
E6
G2
G3
H9
J6
J9
J10
J11
K7
L1
L6
L9
L11
L2 L3
K1 K2 K3
J1 J2
J
3
H1 H2 H3
G1
E5 E2
D2
G7
C3 C2 B1 A8 A9 K6
G5
F5 F1
A2
A3
A5
A6
C10
B11
C11
D11
E11
F11
A1
B2
B3
B4
B5
A4
B6
B7
B9
A10
D10
A7
B8
B10
D9
G6 C8 G10 E7 G9 C4 C5 F10 C6 C7 G11 H11 H10 F6 F7 E10 K5 K10 C9 D3 E3 J4 L10 F3 E9 C1 F9 D1
TCVSS
V-DRIVER ENABLE
(FROM ASIC/DSP)
Figure 83. Typical Circuit Configuration When Using Software Sync Function