Datasheet

AD9923A
Rev. A | Page 57 of 84
10. Generate a SYNC event. If SYNC is high at power-up,
bring SYNC input low for a minimum of 100 ns. Then,
bring SYNC high. This causes the internal counters to
reset and starts a VD/HD operation. The first VD/HD
edge allows VD register updates to occur, including
OUTCONTROL to enable all outputs. If an external
SYNC pulse is not available, generate an internal SYNC
pulse by writing to the SYNCPOL register as described in
the Generating Software Sync Without External Sync
Signal section.
POWER
SUPPLIES
SERIAL
WRITES
VD
(OUTPUT)
1H
FIRST FIELD
SYNC
(INPUT)
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE.
H1/H3, RG, DCLK, STROBE, MSHUT, VSUB
CLI
(INPUT)
HD
(OUTPUT)
t
SYNC
0V
V
H SUPPLY
VL SUPPLY
(HI-Z BY DEFAULT)
(HI-Z BY DEFAULT)
2
34 56779
10
1V
5
1
+3V SUPPLIES
VDR_EN
8
(AND INTERNAL XV1 TO XV13, VSG1 TO VSG8, XSBUCK, XSUBCNT)
0V
+3V
VH
VM
VL
V1 TO V13
VM
05586-073
Figure 75. Recommended Power-Up Sequence and Synchronization, Master Mode
Table 42. Power-Up Register Write Sequence
Register Address Data Description
SW_RST 0x10 0x01 Resets all registers to default values
0x20 to 0xFFF User defined Horizontal, vertical, shutter timing
STANDBY 0x00 0x04 Powers up the AFE
TEST3 0xEA 0x60 Set TEST3 register to required value
OSC_RST 0x16 0x01 Resets crystal oscillator circuit
TGCORE_RSTB 0x15 0x01 Resets internal timing core
MASTER 0x20 0x01 Configures master mode
OUTCONTROL 0x11 0x01 Enables all outputs after SYNC
SYNCPOL 0x13 0x01 SYNC active polarity (for software SYNC only)