Datasheet

AD9923A
Rev. A | Page 40 of 84
VERTICAL DRIVER SIGNAL CONFIGURATION
As shown in Figure 53, XV1 to XV13, VSG1 to VSG8, and
XSUBCK are outputs from the internal AD9923A timing
generator, and V1 to V13 and SUBCK are the resulting outputs
from the AD9923A vertical driver. When VDR_EN = high, the
vertical driver mixes the XV and VSG pulses and amplifies
them to the high voltages required for driving the CCD. Table 2 2
through Table 3 7 describe the output polarities for these signals
vs. their input levels. Refer to these tables when determining the
register settings for the desired output levels. Note that when
VDR_EN = low, V1 to V13 are forced to VM and SUBCK is
forced to VLL. The VDR_EN pin takes priority over the XV and
VSG signals coming from the timing generator.
The VDR_EN pin can be driven either with an external 3 V
logic signal or by one of the AD9923A shutter outputs
(MSHUT, VSUB, STROBE). To make the AD9923A compatible
with existing AD9923 designs, drive the VDR_EN pin with a
diode to either an external 3 V logic signal or to one of the
shutter outputs.
AD9923A
V-DRIVER
3V VH VL
V13
XV13
V10
XV10
V9
XV9
V8
XV8
V6
XV6
V4
XV4
V2
XV2
XV1
VSG1
V1
XV11
VSG2
V11
XV3
VSG3
V3
XV12
VSG4
V12
VSG5
VSG6
XV5
V5A
V5B
VSG7
VSG8
XV7
V7A
V7B
2-LEVEL OUTPUTS
3-LEVEL OUTPUTS
XSUBCK
XSUBCNT
SUBCK
VDR_EN
INTERNAL
TIMING
GENERATOR
05586-052
Figure 53. Internal Vertical Driver Input Signals