Datasheet

AD9923A
Rev. A | Page 17 of 84
HL/H1/H3
H2/H4
RG
NOTES
1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.
CCD
SIGNAL
05586-018
Figure 19. 2-Phase H-Clock Operation
P[0]
PIXEL
PERIOD
RG
HL/H1/H3
P[48] = P[0]
CCD
SIGNAL
P[24]P[12] P[36]
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
POSITION
H2/H4
RGr[0] RGf[12]
Hr[0] Hf[24]
SHP[24]
t
S1
SHD[48]
0
5586-019
Figure 20. High Speed Timing Default Locations
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2
. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
3
. OUTPUT DELAY ( t
OD
) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
P[0]
P[48] = P[0]
PIXEL
PERIOD
P[12]
P[24]
P[36]
DOUT
DCLK
t
OD
05586-020
Figure 21. Digital Output Phase Adjustment