Datasheet

AD9923A
Rev. A | Page 16 of 84
Table 11. Precision Timing Edge Locations
Quadrant Edge Location (Decimal) Register Value (Decimal) Register Value (Binary)
I 0 to 11 0 to 11 000000 to 001011
II 12 to 23 16 to 27 010000 to 011011
III 24 to 35 32 to 43 100000 to 101011
IV 36 to 47 48 to 59 110000 to 111011
P[0] P[48] = P[0]P[12] P[24] P[36]
1 PIXEL
PERIOD
CLI
t
CLIDLY
POSITION
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCK.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (t
CLIDLY
= 6ns TYP).
05586-016
Figure 17. High Speed Clock Resolution from CLI Master Clock Input
H1
H2
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1
RG RISING EDGE.
2
RG FALLING EDGE.
3
SHP SAMPLE LOCATION.
4
SHD SAMPLE LOCATION.
5
HL RISING EDGE POSITION.
6
HL FALLING EDGE POSITION.
7
H1 RISING EDGE POSITION.
8
H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).
9
H3 RISING EDGE POSITION.
10
H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).
H3
H4
3
4
12
78
HL
56
910
05586-017
Figure 18. High Speed Clock Programmable Locations