Datasheet

AD9920A
Rev. B | Page 91 of 112
06878-111
0.1µF
25V
1.0µF
25V
0.1µF
10V
4.7µF
10V
4.7µF
6.3V
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF0.1µF
EXTERNAL RESET IN
V2A
V2B
V3A
V3B
V4 V5 V6 V7
GPO8
GPO7
GPO4 GPO3 GPO2 GPO1
VD
HD
IOVDD
IOVSS
XSUBCNT
V8 V9
V10
V11
V12 V13 V14 V15
DVSS
(LSB) D0
D1
D2
D3
D4
D5
D6
SCK SDATA SL
REFB REFT
CCDIN CLI CLO
CLIVDD
TCVSS
RG
RGVSS
HL
D7
D8
D11 (MSB)
DCLK
H8 H7
H4
H3
H2
H1
LDOIN
LDOOUT
6
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11)
19
3
12
DATA OUTPUTS
DCLK OUTPUT
H1, H2 TO CCD
H3, H4 TO CCD
+3V CLI SUPPLY
H7, H8 TO CCD
H5, H6 TO CCD
SERIAL INTERFACE
(FROM ASIC/DSP)
ANALOG OUTPUT FROM CCD
RG TO CCD
HL TO CCD
AD9920A
NOT DRAWN TO SCALE
VERTICAL SYNC IN/OUT
HORIZONTAL SYNC IN/OUT
0.1uF
+3V SUPPLY
VLL
VL1
VL2
VMM
VM1
VM2
VH1
VH2
VH SUPPLY
VL SUPPLY
VDVDD
V1A
V1B
SUBCK OUTPUT (TO CCD)
SUBCK
VERTICAL OUTPUT (TO CCD)
+3V SUPPLY
XSUBCNT INPUT (FROM GPO OR TIETO +3V)
NC
NC
NC
NC
DVDD
+1.8V SUPPLY
+3V H, RG SUPPL
Y
AVDD
TCVDD
RGVDD
HVDD1
HVDD2
HVSS2
HVSS1
VDR_EN
DRVDD
MASTER CLOCK INPUT (3V LOGIC)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
NC
H6
H5
D9
D10
NC
GPO OUTPUT
DRVSS/LDOVSS
L6
A10
A9
L5
K6
K4
A2
B2
E1
G1
E2
G2
L3
K3
B1
C1
H11
G11
C11
E3 D3
C3
J3
H3
F3
G3
J4
L7 L8 L9
D11
E10
E11
K9
K10
L10
B11
K11
J5
K5
F10
H9
G10
F11
H10
J11
B9
C6
C7
A8
A7
B7
B6
A6
A5
B4 A4 A3
B3
D1
D2
F1
F2
H1
H2
K1
K2 L2
L4
G9
G6 G5
E9
J9
F6
F5
E5
D10
F9
F7 D9
C4
C5
B5
E6
E7
C8
G7
A1
A11
L1
L11
B8
B10
AVSS
CCDGND
AVSS
HVSS2
J2
HVDD2
J1
J7
K7
K8
VDVSS
C10
(TIE TO IOVDD IF RESET IS NOT USED)
J10
NC
+3V
SRSW
SRCTL
C9
C2
J6
V16
J8
GPO OUTPUT
(OR GND, IF NOT USED)
ANALOG CONTROL INPUT
(OR GND, IF NOT USED)
LEGEN
/RST
SYNC
Figure 111. Typical 1.8 V Circuit Configuration in 19-Channel Mode