Datasheet

AD9920A
Rev. B | Page 87 of 112
Table 50. Standby Mode Operation for HCLKMODE = 0x10
(Standby Polarities for XV, XSUBCK, and GPO Outputs Are Programmable)
I/O Block Standby3 (Default)
1, 2
OUT_CONTROL = Low
2
Standby2
3, 4
Standby1
3, 4
AFE Off No change Off Only REFT, REFB on
Timing Core Off No change Off On
CLO Oscillator Off No change Off On
CLO Low No change Low Running
H1 High-Z Low Low (4.3 mA) Low (4.3 mA)
H2 High-Z Low Low (4.3 mA) Low (4.3 mA)
H3 High-Z Low Low (4.3 mA) Low (4.3 mA)
H4 High-Z Low Low (4.3 mA) Low (4.3 mA)
H5 High-Z Low Low (4.3 mA) Low (4.3 mA)
H6 High-Z Low Low (4.3 mA) Low (4.3 mA)
H7 High-Z Low Low (4.3 mA) Low (4.3 mA)
H8 High-Z Low Low (4.3 mA) Low (4.3 mA)
HL High-Z Low Low (4.3 mA) Low (4.3 mA)
RG High-Z Low Low (4.3 mA) Low (4.3 mA)
VD Low
VDHDPOL
value VDHDPOL value
Running
HD Low
VDHDPOL
value VDHDPOL value
Running
DCLK Low Running Low Running
D0 to D11 Low Low Low Low
XV1 to XV24 Low Low Low Low
XSUBCK Low Low Low Low
GPO1 to GPO4,
GPO7, and GPO8
Low Low Low Low
1
To exit Standby3 or Standby2 mode, write 00 to the standby register (Address 0x00, Bits[1:0]) and then reset the timing core after 500 μs to guarantee proper settling of the
oscillator and external crystal.
2
Standby3 mode takes priority over OUT_CONTROL for determining the output polarities.
3
These polarities assume OUT_CONTROL = high because OUT_CONTROL = low takes priority over Standby1 and Standby2.
4
Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).