Datasheet

AD9920A
Rev. B | Page 75 of 112
1
2
3
1
SYNC_MASK_VD REGISTER ENABLES MASKING OF VD DURING SYNCSUSPEND WHEN SET HIGH (DEFAULT).
2
SYNC_MASK_HD REGISTER ENABLES MASKING OF HD DURING SYNCSUSPEND WHEN SET HIGH (DEFAULT).
3
V-OUTPUT PULSES CONTINUE IN SEQUENCE.
VDLEN
SYNC
VD
HD
SCP
XV1 TO XV24
06878-096
Figure 96. Enhanced SYNC Mode 3
111 111
NOTES
1. VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) ARE DISABLED DURING THE SYNC INTERVAL.
SYNC
VD
1
VD REGISTERS ARE UPDATED HERE.
06878-097
Figure 97. Register Update Behavior
5
1
FIELD DESIGNATOR IS INCREMENTED ON BOTH SYNC EDGES.
57 3 7
SYNC
VD
FIELD
DESIGNATOR
1 1
06878-098
Figure 98. Enhanced SYNC Mode Effect on Field Designator