Datasheet

AD9920A
Rev. B | Page 5 of 112
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD1 and HVDD2 = 2.7 V to 3.6 V, C
L
= 20 pF, T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS (IOVDD)
High Level Input Voltage V
IH
V
DD
− 0.6 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 μA
Low Level Input Current I
IL
10 μA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS (IOVDD, DRVDD)
High Level Output Voltage V
OH
I
OH
= 2 mA V
DD
− 0.5 V
Low Level Output Voltage V
OL
I
OL
= 2 mA 0.5 V
RG and H-DRIVER OUTPUTS (HVDD1,
HVDD2, and RGVDD)
High Level Output Voltage V
OH
Maximum current V
DD
− 0.5 V
Low Level Output Voltage V
OL
Maximum current 0.5 V
Maximum H1 to H8 Output Current Programmable 30 mA
Maximum HL and RG Output Current Programmable 17 mA
Maximum Load Capacitance Each output 60 pF
CLI INPUT With CLO oscillator disabled
High Level Input Voltage V
IHCLI
CLIVDD/2 + 0.5 V
Low Level Input Voltage V
ILCLI
CLIVDD/2 − 0.5 V
ANALOG SPECIFICATIONS
AVDD = 1.8 V, f
CLI
= 40.5 MHz, typical timing specifications, T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
CDS
1
DC Restore AVDD − 0.5 V 1.21 1.3 1.44 V
Allowable CCD Reset Transient Limit is the lower of AVDD + 0.3 V or 2.2 V 0.5 0.8 V
CDS Gain Accuracy VGA gain = 6.3 dB (Code 15, default value)
−3 dB CDS Gain −3.1 −2.6 −2.1 dB
0 dB CDS Gain −0.6 −0.1 +0.4 dB
+3 dB CDS Gain 2.7 3.2 3.7 dB
+6 dB CDS Gain 5.2 5.7 6.2 dB
Maximum Input Range Before
Saturation
−3 dB CDS Gain 1.4 V p-p
0 dB CDS Gain 1.0 V p-p
+3 dB CDS Gain 0.7 V p-p
+6 dB CDS Gain 0.5 V p-p
Allowable OB Pixel Amplitude
1
0 dB CDS Gain (Default) −100 +200 mV
+6 dB CDS Gain −50 +100 mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Low Gain VGA Code 15, default 6.3 dB
Maximum Gain VGA Code 1023 42.4 dB