Datasheet

AD9920A
Rev. B | Page 11 of 112
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BOTTOM VIEW
(Not to Scale)
1110987654321
A
B
C
D
E
F
G
H
J
K
L
A
1 CORNER
INDEX AREA
06878-004
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
L6 AVDD P Analog Supply.
J7, K8 AVSS P Analog Supply Ground.
A10 DVDD P Digital Logic Supply.
A9 DVSS P Digital Logic Ground.
L5 CLIVDD P CLI Input Supply.
K6 TCVDD P Analog Timing Core Supply.
K4 TCVSS P Analog Timing Core Ground.
A2 DRVDD P Data Driver Supply.
B2 DRVSS/LDOVSS P Data Driver and LDO Ground.
E1 HVDD1 P H-Driver Supply.
E2 HVSS1 P H-Driver Ground.
G1 HVDD2 P H-Driver Supply.
G2 HVSS2 P H-Driver Ground.
J1 HVDD2 P H-Driver Supply.
J2 HVSS2 P H-Driver Ground.
L3 RGVDD P RG, HL Driver Supply.
K3 RGVSS P RG, HL Driver Ground.
B1 LDOIN P LDO 3.3 V Input.
C1 LDOOUT P LDO Output Voltage.
H11 IOVDD P Digital I/O Supply.
G11 IOVSS P Digital I/O Ground.
C11 VDVDD P V-Driver Logic Supply (3 V).
C10 VDVSS P V-Driver Ground.
E3 VM1 P V-Driver Midsupply.
D3 VL1 P V-Driver Low Supply.
C3 VH1 P V-Driver High Supply.
J3 VH2 P V-Driver High Supply.
H3 VL2 P V-Driver Low Supply.
F3 VM2 P V-Driver Midsupply.
G3 VMM P V-Driver Midsupply for SUBCK Output.
J4 VLL P V-Driver Low Supply for SUBCK Output.
L7 CCDIN AI CCD Signal Input.
K7 CCDGND AI CCD Ground.
C2 SRCTL AI Slew Rate Control Pin. Tie to VDVSS if not used.
L8 REFT AO Voltage Reference Top Bypass.
L9 REFB AO Voltage Reference Bottom Bypass.
D11 VD DIO Vertical Sync Pulse.
E10 HD DIO Horizontal Sync Pulse.