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ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 12 Bit CSPBGA 105
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AD9920A
Rev. B | Page 104 of 112
Address
Data
Bits
Default
Value
Update
Type Name Description
0x9E [12:0] 0 VD GP6_TOG3_PX General-Purpose Signal 6, third toggle position, pixel location.
[25:13] 0 GP6_TOG4_FD General-Purpose Signal 6, fourth toggle position, field location.
0x9F [12:0] 0 VD GP6_TOG4_LN General-Purpose Signal 6, fourth toggle position, line location.
[25:13] 0 GP6_TOG4_PX General-Purpose Signal 6, fourth toggle position, pixel location.
0xA0 [12:0] 0 VD GP7_TOG1_FD General-Purpose Signal 7, first toggle position, field location.
[25:13] 0 GP7_TOG1_LN General-Purpose Signal 7, first toggle position, line location.
0xA1 [12:0] 0 VD GP7_TOG1_PX General-Purpose Signal 7, first toggle position, pixel location.
[25:13] 0 GP7_TOG2_FD General-Purpose Signal 7, second toggle position, field location.
0xA2 [12:0] 0 VD GP7_TOG2_LN General-Purpose Signal 7, second toggle position, line location.
[25:13] 0 GP7_TOG2_PX General-Purpose Signal 7, second toggle position, pixel location.
0xA3 [12:0] 0 VD GP7_TOG3_FD General-Purpose Signal 7, third toggle position, field location.
[25:13] 0 GP7_TOG3_LN General-Purpose Signal 7, third toggle position, line location.
0xA4 [12:0] 0 VD GP7_TOG3_PX General-Purpose Signal 7, third toggle position, pixel location.
[25:13] 0 GP7_TOG4_FD General-Purpose Signal 7, fourth toggle position, field location.
0xA5 [12:0] 0 VD GP7_TOG4_LN General-Purpose Signal 7, fourth toggle position, line location.
[25:13] 0 GP7_TOG4_PX General-Purpose Signal 7, fourth toggle position, pixel location.
0xA6 [12:0] 0 VD GP8_TOG1_FD General-Purpose Signal 8, first toggle position, field location.
[25:13] 0 GP8_TOG1_LN General-Purpose Signal 8, first toggle position, line location.
0xA7 [12:0] 0 VD GP8_TOG1_PX General-Purpose Signal 8, first toggle position, pixel location.
[25:13] 0 GP8_TOG2_FD General-Purpose Signal 8, second toggle position, field location.
0xA8 [12:0] 0 VD GP8_TOG2_LN General-Purpose Signal 8, second toggle position, line location.
[25:13] 0 GP8_TOG2_PX General-Purpose Signal 8, second toggle position, pixel location.
0xA9 [12:0] 0 VD GP8_TOG3_FD General-Purpose Signal 8, third toggle position, field location.
[25:13] 0 GP8_TOG3_LN General-Purpose Signal 8, third toggle position, line location.
0xAA [12:0] 0 VD GP8_TOG3_PX General-Purpose Signal 8, third toggle position, pixel location.
[25:13] 0 GP8_TOG4_FD General-Purpose Signal 8, fourth toggle position, field location.
0xAB [12:0] 0 VD GP8_TOG4_LN General-Purpose Signal 8, fourth toggle position, line location.
[25:13] 0 GP8_TOG4_PX General-Purpose Signal 8, fourth toggle position, pixel location.
0xAC [7:0] 0 VD GP_LN_MODE 1 = outputs specified GP pulse on every line.
0xAD [27] 0 VD UNUSED Do not access, or set to 0.
0xAE [27] 0 VD UNUSED Do not access, or set to 0.
0xAF [27] 0 VD UNUSED Do not access, or set to 0.
Table 60. Update Control Registers
Address
Data
Bits
Default
Value
Update
Type Name Description
0xB0 [15:0] 0x5803 SCK AFE_UPDT_SCK Each bit corresponds to one address location.
Bit 0: 1 = update Address 0x00 on SL rising edge.
Bit 1: 1 = update Address 0x01 on SL rising edge.
Bit 15: 1 = update Address 0x0F on SL rising edge.
0xB1 [15:0] 0xA7FC SCK AFE_UPDT_VD Each bit corresponds to one address location.
Bit 0: 1 = update Address 0x00 on VD rising edge.
Bit 1: 1 = update Address 0x01 on VD rising edge.
Bit 15: 1 = update Address 0x0F on VD rising edge.
0xB2 [15:0] 0xD8FD SCK MISC_UPDT_SCK Enable SCK update of miscellaneous registers, Address 0x10 to Address 0x1F.
0xB3 [15:0] 0x2702 SCK MISC_UPDT_VD Enable VD update of miscellaneous registers, Address 0x10 to Address 0x1F.
0xB4 [15:0] 0xFFF9 SCK VDHD_UPDT_SCK Enable SCK update of VD/HD registers, Address 0x20 to Address 0x2F.
0xB5 [15:0] 0x0006 SCK VDHD_UPDT_VD Enable VD update of VD/HD registers, Address 0x20 to Address 0x2F.
0xB6 [15:0] 0xFFFF SCK TC_UPDT_SCK Enable SCK update of timing core registers, Address 0x30 to Address 0x3F.
0xB7 [15:0] 0000 SCK TC_UPDT_VD Enable VD update of timing core registers, Address 0x30 to Address 0x3F.
0xB8 [27:0] 0x04 Test Test register. Do not access, or write to 0x04.
0xB9 [27:0] 0 UNUSED Do not access, or write to 0x00.