2-Bit CCD Signal Processor with V-Driver and Precision Timing Generator AD9920A FEATURES GENERAL DESCRIPTION Integrated 19-channel V-driver 1.8 V AFETG core 24 programmable vertical clock signals Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB, and +6 dB gain 12-bit, 40.
AD9920A TABLE OF CONTENTS Features .............................................................................................. 1 V-Driver Slew Rate Control ...................................................... 60 Applications ....................................................................................... 1 Shutter Timing Control ............................................................. 60 General Description .........................................................................
AD9920A REVISION HISTORY 6/10—Rev. A to Rev. B Changes to Figure 1........................................................................... 1 Changes to Figure 9, Figure 10, Figure 12, and Figure 13 .........15 Moved Terminology Section..........................................................16 Changes to Figure 15 ......................................................................17 Moved Generating HBLK Line Alternation Section ..................24 Moved Figure 32 ...................................
AD9920A SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE INPUTS AVDD TCVDD CLIVDD RGVDD HVDD1 and HVDD2 DVDD DRVDD IOVDD V-DRIVER POWER SUPPLY VOLTAGES VDVDD VH1, VH2 VL1, VL2 VM1, VM2 VLL VH1, VH2 to VL1, VL2, VLL VMM 1 LDO 2 LDOIN Output Voltage Output Current POWER SUPPLY CURRENTS—40.
AD9920A DIGITAL SPECIFICATIONS IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD1 and HVDD2 = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 2.
AD9920A Parameter BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level Maximum Clamp Level ADC Resolution Differential Nonlinearity (DNL) 2 No Missing Codes Integral Nonlinearity (INL)2 Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain Maximum Gain Peak Nonlinearity, 1 V Input Signal2 Total Output Noise2 Power Supply Rejection (PSR)2 2 Min Typ Measured at ADC output Code 0 Code 1023 Max S
AD9920A TIMING SPECIFICATIONS CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, fCLI = 40.5 MHz, unless otherwise noted. Table 4.
AD9920A VERTICAL DRIVER SPECIFICATIONS VH1, VH2 = 12 V; VM1, VM2, VMM = 0 V; VL1, VL2, VLL = −6 V; CL shown in load model; TA = 25°C. Table 5. Parameter V1A TO V13 Symbol Delay Time, VL to VM and VM to VH Delay Time, VM to VL and VH to VM Rise Time, VL to VM Rise Time, VM to VH Fall Time, VM to VL Fall Time, VH to VM Output Currents At −7.25 V At −0.25 V At +0.25 V At +14.
AD9920A 50% 50% tRLM, tRMH, tRLH 90% V-DRIVER OUTPUT tPML, tPHM , tPHL 90% tPLM, tPMH, tPLH 10% tFML, tFHM, tFHL 10% Figure 3. Definition of V-Driver Timing Specifications Rev.
AD9920A ABSOLUTE MAXIMUM RATINGS Table 6.
AD9920A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A1 CORNER INDEX AREA 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K 06878-004 L BOTTOM VIEW (Not to Scale) Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin No.
AD9920A Pin No.
AD9920A Pin No. D9 C4 C5 B5 E6 E7 C8 J8 Mnemonic V9 V10 V11 V12 V13 V14 V15 V16 Type 1 VO2 VO2 VO2 VO2 VO2 VO2 VO2 VO2 G7 A1, A11, B8, B10, J10, L1, L11 SUBCK NC VO3 1 Description CCD Vertical Transfer Clock. Two-level output (XV9). CCD Vertical Transfer Clock. Two-level output (XV10). CCD Vertical Transfer Clock. Two-level output (XV11). CCD Vertical Transfer Clock. Two-level output (XV12). CCD Vertical Transfer Clock. Two-level output (XV13). CCD Vertical Transfer Clock. Two-level output (XV14).
AD9920A TYPICAL PERFORMANCE CHARACTERISTICS 400 3.0 3.3V, 2.0V 350 2.5 3.0V, 1.8V 2.0 250 INL (LSB) 1.5 200 1.0 150 0.5 100 0 50 –0.5 0 18 32 06878-007 2.7V, 1.6V 06878-005 POWER (mW) 300 –1.0 40 0 0.5k FREQUENCY (MHz) 0.8 45 0.6 40 0.2 0 –0.2 –0.4 30 15 5 2.5k 4.0k 3.0k 3.5k 4.0k ADC OUTPUT CODE Figure 6. Typical Differential Nonlinearity (DNL) Performance 0dB CDS GAIN +3dB CDS GAIN +6dB CDS GAIN 20 10 2.0k 3.5k –3dB CDS GAIN 25 –0.8 1.5k 3.0k 35 –0.
AD9920A EQUIVALENT CIRCUITS IOVDD AVDD R 330Ω DIGITAL INPUTS AVSS 06878-012 AVSS 06878-009 CCDIN IOVSS Figure 12. Digital Inputs Figure 9. CCDIN DVDD HVDD OR RGVDD DRVDD DATA RG, HL, H1 TO H8 D0 TO D11 DRVSS 06878-010 DVSS OUTPUT THREE-STATE Figure 10. Digital Data Outputs 06878-013 THREESTATE HVSS OR RGVSS Figure 13. H1 to H8, HL, RG Drivers VDVDD VDVDD 3.5kΩ 3.5kΩ XSUBCNT VDR_EN VDVSS Figure 11. XSUBCNT Figure 14. VDR_EN Rev.
AD9920A TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, each for its respective input, must be present over all operating conditions.
AD9920A THEORY OF OPERATION Figure 15 shows the typical system block diagram for the AD9920A in master mode. The CCD output is processed by the AD9920A AFE circuitry, which consists of a CDS, black level clamp, and ADC. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9920A from the system microprocessor through the 3-wire serial interface.
AD9920A HIGH SPEED PRECISION TIMING CORE The AD9920A generates high speed timing signals using the flexible Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE; it includes the reset gate (RG), horizontal drivers (H1 to H8, HL), and SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
AD9920A H-Driver and RG Outputs In addition to the programmable timing positions, the AD9920A features on-chip output drivers for the RG, HL, and H1 to H8 outputs. These drivers are powerful enough to drive the CCD inputs directly. The H-driver and RG current can be adjusted for optimum rise/fall time for a particular load by using the drive strength control registers (Address 0x36 and Address 0x37). The 3-bit drive setting for each H1 to H8 output is adjustable in 4.3 mA increments: 0 = off, 1 = 4.
AD9920A 1 2 H1, H3, H5, H7 4 3 H2, H4, H6, H8 06878-020 H1 TO H8 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H2 RISING EDGE. 4H2 FALLING EDGE. Figure 20. HCLK Mode 2 Operation 1 2 H1, H3 H2, H4 3 4 H5, H7 H1 TO H8 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H5 RISING EDGE. 4H5 FALLING EDGE. 06878-021 H6, H8 Figure 21. HCLK Mode 3 Operation 1 2 H1, H2 3 4 H5, H6 5 6 H7, H8 H1 TO H8 PROGRAMMABLE LOCATIONS: FALLING EDGE. RISING EDGE. FALLING EDGE.
AD9920A POSITION P[0] P[16] RGr[0] RGf[16] P[32] P[48] P[64] = P[0] CLI RG H1r[0] H1f[32] tSHDINH H1 tSHDINH H2 tS2 tS1 CCD SIGNAL SHPLOC[32] tSHPINH SHP 62 50 SHDLOC[0] SHD 1 DOUTPHASEP 12 tDOUTINH 06878-023 NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD. TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN. 2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS. 3.
AD9920A Normally, the data output and DCLK signals track in phase, based on the contents of the DOUTPHASE registers. The DCLK output phase can also be held fixed with respect to the data outputs by setting the DCLKMODE register high (Address 0x39, Bit 16). In this mode, the DCLK output remains at a fixed phase equal to a delayed version of CLI, and the data output phase remains programmable.
AD9920A HORIZONTAL CLAMPING AND BLANKING CLPOB and PBLK Masking Areas The horizontal clamping and blanking pulses of the AD9920A are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK in the different regions of each field. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts.
AD9920A HD 2 CLPOB 1 PBLK 3 ACTIVE ACTIVE 06878-027 PROGRAMMABLE SETTINGS: 1START POLARITY (CLAMP AND 2FIRST TOGGLE POSITION. 3SECOND TOGGLE POSITION. BLANK REGION ARE ACTIVE LOW). Figure 27. Clamp and Preblank Pulse Placement NO CLPOB SIGNAL FOR LINES 6 TO 8 VD 0 1 NO CLPOB SIGNAL FOR LINE 600 2 597 598 HD CLPMASKSTART1 = 6 CLPMASKEND1 = 9 CLPMASKSTART2 = 600 CLPMASKEND2 = 601 06878-028 CLPOB Figure 28.
AD9920A HD HBLKEND BLANK HBLK BLANK 06878-118 HBLKSTART BASIC HBLK PULSE IS GENERATED USING HBLKSTART AND HBLKEND REGISTERS Figure 29. Typical Horizontal Blanking Pulse Placement (HBLK_MODE = 0) HD HBLK H1/H3/H5/H7 THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS PROGRAMMABLE (H2/H4/H6/H8 AND HL ARE SEPARATELY PROGRAMMABLE) 06878-029 H1/H3/H5/H7 H2/H4/H6/H8 Figure 30.
AD9920A Table 12.
AD9920A Register HBLKSTARTA HBLKSTARTB HBLKSTARTC HBLKALT_PAT0 Length (Bits) 13 13 13 3 Range 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 5 even repeat area HBLKALT_PAT1 HBLKALT_PAT2 HBLKALT_PAT3 HBLKALT_PAT4 HBLKALT_PAT5 3 3 3 3 3 0 to 5 even repeat area 0 to 5 even repeat area 0 to 5 even repeat area 0 to 5 even repeat area 0 to 5 even repeat area 1 PIXEL Description HBLK Repeat Area Start Position A for HBLK Mode 1. Set to 8191 if not used.
AD9920A 1 PIXEL 1 PIXEL 1 PIXEL A1 PHASE 1 1 PIXEL 1 PIXEL B1 PHASE 2 B2 A2 PHASE 3 A3 B3 INTERNAL DIGITAL CLOCK A MASTER BLANKING SIGNAL B MASK LEVEL = HIGH H1/H2 H5/H6 MASK LEVEL = LOW MASK LEVEL = HIGH H7/H8 06878-033 BLANKING Figure 34.
AD9920A Increasing H-Clock Width During HBLK HBLK Mode 1 Operation The AD9920A allows the H1 to H8 pulse width to be increased during the HBLK interval. As shown in Figure 36, the H-clock frequency can be reduced by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable this feature, the HCLK_WIDTH register (Address 0x35, Bits[7:4]) is set to a value between 1 and 15. When this register is set to 0, the wide HCLK feature is disabled.
AD9920A HD HBLKLEN HBLK HBLKSTARTA ALL RAxHxREPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES HBLKSTARTB HBLKSTARTC H1 RA0H1REPA RA0H1REPB RA0H1REPC RA1H1REPA RA1H1REPB RA1H1REPC RA1H2REPA RA1H2REPB RA1H2REPC H2 RA0H2REPA RA0H2REPB RA0H2REPC HBLKEND REPEAT AREA 1 REPEAT AREA 0 HBLKREP = 2 TO CREATE TWO REPEAT AREAS Figure 38. HBLK Mode 1 Operation As shown in Figure 38, setting the RAxH1REPA/B/C or RAxH2REPA/B/C register to 0 masks HCLK groups from appearing in a particular repeat area.
AD9920A 2 VERTICAL OB LINES V EFFECTIVE IMAGE AREA 10 VERTICAL OB LINES H 48 OB PIXELS 4 OB PIXELS 06878-038 HORIZONTAL CCD REGISTER 28 DUMMY PIXELS Figure 39. Example CCD Configuration OPTICAL BLACK OPTICAL BLACK HD CCD OUTPUT VERTICAL SHIFT DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERTICAL SHIFT SHP SHD H1/H3/H5/H7 H2/H4/H6/H8 HBLK PBLK NOTES 1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW). Figure 40. Horizontal Sequence Example Rev.
AD9920A 2. VERTICAL TIMING GENERATION The AD9920A provides a flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The vertical transfer clocks are used to shift each line of pixels into the horizontal output register of the CCD. The AD9920A allows these outputs to be individually programmed into various readout configurations by using a four-step process. Figure 41 shows an overview of how the vertical timing is generated in four steps. 3.
AD9920A Vertical Pattern Groups (VPAT) The vertical pattern groups define the individual pulse patterns for each XV1 to XV24 output signal. Table 14 summarizes the registers available for generating each V-pattern group. The first, second, third, and fourth toggle positions (VTOG1, VTOG2, VTOG3, and VTOG4) are the pixel locations within the line where the pulse transitions. All toggle positions are 13-bit values, allowing their placement anywhere in the first 8191 pixels of the line.
AD9920A Generally, the same number of repetitions is programmed into both registers. If a different number of repetitions is required on odd and even lines, separate values can be used for each register (see the Generating Line Alternation for V-Sequences and HBLK section). The VSTARTA, VSTARTB, VSTARTC, and VSTARTD registers specify where in the line the V-pattern group starts.
AD9920A Table 15. Summary of V-Sequence Registers (see Table 11 and Table 12 for the CLPOB, PBLK, and HBLK Register Summary) Register HOLD Length (Bits) 4 CONCAT_GRP 4 VREP_MODE 2 LASTREPLEN_EN 4 HDLENE HDLENO VPOL GROUPSEL_0 14 14 24 24 GROUPSEL_1 24 VPATSELA VPATSELB VPATSELC VPATSELD VSTARTA VSTARTB VSTARTC VSTARTD VLENA VLENB VLENC VLEND VREPA_1 VREPA_2 VREPA_3 VREPA_4 5 5 5 5 13 13 13 13 13 13 13 13 13 13 13 13 Description Use in conjunction with VMASK_EVEN and VMASK_ODD.
AD9920A Register VREPB_ODD VREPC_ODD VREPD_ODD VREPB_EVEN VREPC_EVEN VREPD_EVEN FREEZE1 Length (Bits) 13 13 13 13 13 13 13 FREEZE2 13 FREEZE3 13 FREEZE4 13 RESUME1 13 RESUME2 13 RESUME3 13 RESUME4 13 LASTREPLEN_A 13 LASTREPLEN_B 13 LASTREPLEN_C 13 LASTREPLEN_D 13 VSEQALT_EN VALTSEL0_EVEN 1 18 VALTSEL1_EVEN 18 VALTSEL0_ODD 18 VALTSEL1_ODD 18 SPC_PAT_EN 3 SEQ_ALT_INC 1 SEQ_ALT_RST 1 Description Number of repetitions for the V-pattern Group B for odd lines.
AD9920A HD XV1 TO XV8 USE V-PATTERN GROUP A XV1 XV8 XV9, XV10 USE V-PATTERN GROUP B 06878-043 XV9 XV10 Figure 44. Using Separate Group A and Group B Patterns HD V-PATTERN GROUP A V-PATTERN GROUP B V-PATTERN GROUP C V-PATTERN GROUP D 06878-044 XV1 XV24 Figure 45. Combining Multiple V-Patterns Using CONCAT_GRP = 1 HD V-PATTERN GROUP A V-PATTERN GROUP B XV1 GROUP A REP 1 GROUP A REP 2 GROUP A REP 3 06878-045 XV10 Figure 46.
AD9920A If only two groups are needed (up to eight toggle positions) for the specified timing, the VPATSELB, VPATSELC, and VPATSELD registers can be programmed to the same value. If only three groups are needed, VPATSELC and VPATSELD can be programmed to the same value. Following this approach conserves register memory if the four separate V-patterns are not needed. Note that when CONCAT_GRP is enabled, the Group A settings are used only for start position, polarity, length, and repetitions.
AD9920A V-PATTERN A V-PATTERN B VLENA VLENB V-PATTERN C V-PATTERN D XV1 XV2 XV3 XV23 VLEND 06878-046 VLENC NOTES 1. EACH SEGMENT MUST BE THE SAME LENGTH. VLENA = VLENB = VLENC = VLEND. Figure 47. Vertical Timing Divided into Four Segments: VPATA, VPATB, VPATC, and VPATD HD COMBINED V-PATTERN A B B D A C C B C B D A B A A A 06878-047 NOTES 1. ABLE TO CONCATENATE PATTERNS TOGETHER ARBITRARILY. 2. EACH PATTERN CAN HAVE UP TO FOUR TOGGLES PROGRAMMED. 3.
AD9920A Using the LASTREPLEN_EN Register The LASTREPLEN_EN register (Address 0x00, Bits[19:16] in the V-sequence registers) is used to enable a separate pattern length to be used in the final repetition of several pulse repetitions.
AD9920A Vertical Masking Using the FREEZE/RESUME Registers Four sets of FREEZE/RESUME registers are provided, allowing the vertical outputs to be interrupted up to four times in the same line. As shown in Figure 51 and Figure 52, the FREEZE/RESUME registers are used to temporarily mask the V-outputs. The pixel locations to begin the masking (FREEZE) and end the masking (RESUME) create an area in which the vertical toggle positions are ignored.
AD9920A Hold Area Using the FREEZE/RESUME Registers The FREEZE/RESUME registers can also be used to create a hold area in which the V-outputs are temporarily held and later continued, starting at the point where they were held. As shown in Figure 53, the hold area function is different from the vertical HD FREEZE masking function in that the V-outputs continue from where they stopped rather than continuing from where they would have been.
AD9920A Special Pattern Insertion has been added into the middle of the sequence. Figure 55 shows more detail on how to set the registers to achieve the desired timing. Additional flexibility is available using the SPC_PAT_EN register bits, which allow a Group B, Group C, or Group D pattern to be inserted into a series of Group A repetitions. This feature is useful when a different pattern is needed at the start, middle, or end of a sequence.
AD9920A Sequence Line Alternation that line the sequence number automatically increments to Sequence 3. In the same way, at the end of that line, the sequence number automatically increments to Sequence 4. To support the timing requirements of some advanced CCDs in a memory-efficient manner, the AD9920A can automatically increment the sequence number at the end of a given line through the use of the SEQ_ALT_INC register (V-Sequence Register 0x09, Bit 20).
AD9920A Complete Field: Combining V-Sequences The HDLASTLEN register specifies the number of pixels in the last line of the field. After the V-sequences are created, they are combined to create different readout fields. A field consists of up to nine regions; within each region, a different V-sequence can be selected. Figure 57 shows how the sequence change positions (SCPs) designate the line boundary for each region and how the SEQ registers then select which V-sequence is used in each region.
AD9920A SCP1 SCP0 SCP2 SCP4 SCP3 SCP5 SCP8 VD REGION 0 REGION 1 REGION 2 REGION 3 REGION 4 REGION 8 SEQ0 SEQ1 SEQ2 SEQ3 SEQ4 SEQ8 HD XV1 TO XVx SGACTLINE1 VSG 06878-056 FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD. 2. SEQ0 TO SEQ8 SELECT THE DESIRED V-SEQUENCE FOR EACH REGION. 3. SGACTLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR GATE PULSE(S). Figure 57.
AD9920A Multiplier Mode To calculate the exact toggle position, which is counted in pixels after the start position, use the following equation: To generate very wide vertical timing pulses, a vertical region can be configured into a multiplier region. This mode uses the V-pattern registers in a slightly different manner. Multiplier mode can be used to support unusual CCD timing requirements, such as vertical pulses that are wider than the 13-bit V-pattern toggle position counter.
AD9920A Vertical Sensor Gate (Shift Gate) Patterns Note that only two of the four V-pattern toggle positions are available when a vertical signal is selected to be a VSG pulse. In an interline CCD, the vertical sensor gate (VSG) pulses are used to transfer the pixel charges from the light-sensitive image area into light-shielded vertical registers.
AD9920A Mode Registers The mode registers are used to select the field timing of the AD9920A. Typically, all of the field, V-sequence, and V-pattern information is programmed into the AD9920A at startup. During operation, the mode registers allow the user to select any combination of field timing to meet the requirements of the system. The advantage of using the mode registers in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation.
AD9920A EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD1, SECOND FIELD = FIELD2, THIRD FIELD = FIELD3 MODE SETTINGS: 0x2A = 0x03 0x2B = 0x820 0x2C = 0x00 FIELD1 FIELD2 FIELD3 EXAMPLE 2: TOTAL FIELDS = 1, FIRST FIELD = FIELD3 MODE SETTINGS: 0x2A = 0x01 0x2B = 0x03 0x2C = 0x00 FIELD3 EXAMPLE 3: TOTAL FIELDS = 4, FIRST FIELD = FIELD5, SECOND FIELD = FIELD1, THIRD FIELD = FIELD4, FOURTH FIELD = FIELD2 MODE SETTINGS: 0x2A = 0x04 0x2B = 0x11025 0x2C = 0x00 FIELD1 FIELD2 FIELD4 06878-062 FIELD5 Figure 61
AD9920A VERTICAL TIMING EXAMPLE To better understand how the AD9920A vertical timing generation is used, consider the example CCD timing chart in Figure 64. This example illustrates a CCD using a general three-field readout technique. As shown in Figure 64, each readout field must be divided into separate regions to perform each step of the readout. The sequence change positions (SCPs) determine the line boundaries for each region, and the SEQ registers assign a particular V-sequence to each region.
Rev. B | Page 52 of 112 Figure 64.
AD9920A INTERNAL VERTICAL DRIVER CONNECTIONS (18-CHANNEL MODE) AD9920A V-DRIVER +3V XV16 (XSG1) VH,VL G9 V1A XV1 G6 XV17 (XSG2) XV18 (XSG3) G5 V1B V2A XV2 E9 XV19 (XSG4) XV20 (XSG5) J9 V2B V3A 3-LEVEL OUTPUTS XV3 F6 XV21 (XSG6) XV4 F5 V3B V4 XV22 (XSG7) XV5 E5 V5 XV23 (XSG8) XV6 D10 V6 XV24 (XSG9) XV7 F9 XV8 F7 XV9 D9 XV10 C4 XV11 C5 XV12 B5 XV13 E6 XV14 E7 XV15 C8 J8 XSUBCK G7 K11 V7 V8 V9 V10 V11 V12 V13 V14 V15 2-LEVEL OUTPUT, REDUCED DRIVE V16 SUB
AD9920A INTERNAL VERTICAL DRIVER CONNECTIONS (19-CHANNEL MODE) AD9920A V-DRIVER XV16 (XSG1) +3V VH,VL G9 V1A XV1 G6 XV17 (XSG2) XV18 (XSG3) G5 V1B V2A XV2 E9 XV19 (XSG4) XV3 J9 V2B V3A XV20 (XSG5) 3-LEVEL OUTPUTS XV23 F6 XV21 (XSG6) XV4 F5 V3B V4 XV22 (XSG7) XV5 E5 V5 GPO5 (XSG8) INTERNAL TIMING GENERATOR XV6 D10 V6 GPO6 (XSG9) XV7 F9 XV8 F7 XV9 D9 XV10 C4 XV11 C5 XV12 B5 XV13 E6 XV14 E7 XV15 C8 XV24 J8 XSUBCK V7 V8 V9 V10 2-LEVEL OUTPUTS V11 V12 V13
AD9920A OUTPUT POLARITY OF VERTICAL TRANSFER CLOCKS AND SUBSTRATE CLOCK Table 23. V1A Output Polarity Table 29. V4 Output Polarity Vertical Driver Input LEGEN X X X X XV1 L L H H XV16 (XSG1) L H L H Vertical Driver Input V1A Output VH VM VL VL Table 24. V1B Output Polarity LEGEN X X X X X X X X XV1 L L H H XV17 (XSG2) L H L H V1B Output VH VM VL VL Table 25.
AD9920A Table 35. V10 Output Polarity Table 40. V15 Output Polarity Vertical Driver Input LEGEN X X XV10 L H Vertical Driver Input V10 Output VM VL Table 36. V11 Output Polarity LEGEN X X X X XV11 L H Vertical Driver Input V11 Output VM VL Table 37. V12 Output Polarity X X XV12 L H V12 Output VM VL Table 38. V13 Output Polarity Vertical Driver Input LEGEN X X XV13 L H LEGEN L H H Vertical Driver Input LEGEN X X X X V13 Output VM VL Table 39.
AD9920A XV1 XV16 (XSG1) VH VM 06878-066 V1A VL Figure 67. XV1, XV16, and V1A Output Polarities XV1 XV17 (XSG2) VH VM 06878-067 V1B VL Figure 68. XV1, XV17, and V1B Output Polarities XV2 XV18 (XSG3) VH VM 06878-068 V2A VL Figure 69. XV2, XV18, and V2A Output Polarities XV2 XV19 (XSG4) VH VM 06878-069 V2B VL Figure 70. XV2, XV19, and V2B Output Polarities Rev.
AD9920A XV3 XV20 (XSG5) VH VM 06878-070 V3A VL Figure 71. XV3, XV20, and V3A Output Polarities XV3 XV21 (XSG6) VH VM 06878-071 V3B VL Figure 72. XV3, XV21, and V3B Output Polarities (LEGEN = Low) XV23 XV21 (XSG6) VH VM 06878-072 V3B VL Figure 73. XV23, XV21, and V3B Output Polarities (LEGEN = High) XV4 XV22 (XSG7) VH VM 06878-073 V4 VL Figure 74. XV4, XV22, and V4 Output Polarities Rev.
AD9920A XV5 XV23 (XSG8) VH V5 06878-074 VM VL Figure 75. XV5, XV23, and V5 Output Polarities (LEGEN = Low) XV5 GPO5 (XSG8) VH V5 06878-075 VM VL Figure 76. XV5, GPO5, and V5 Output Polarities (LEGEN = High) XV6 GPO6 (XSG9) VH V6 06878-077 VM VL Figure 77. XV6, GPO6, and V6 Output Polarities (LEGEN = High) XV7, XV8, XV9, XV10, XV11, XV12, XV13, XV14, XV15 06878-078 VM V7, V8, V9, V10, V11, V12, V13, V14, V15 VL Figure 78.
AD9920A XSUBCNT XSUBCK VH VMM 06878-080 SUBCK VLL Figure 80. XSUBCNT, XSUBCK, and SUBCK Output Polarities V-DRIVER SLEW RATE CONTROL SUBSTRATE CLOCK OPERATION (SUBCK) The AD9920A allows the user to moderate the slew rates of the V-driver outputs when transitioning to VM and VL (this feature does not affect transitions to VH). This feature minimizes coupling from V-driver activity that occurs while the AD9920A is clocking valid image pixel data out of the CCD.
AD9920A SUBCK High Precision Operation High precision shuttering is used in the same manner as normal shuttering, but it uses an additional register to control the last SUBCK pulse. In this mode, the SUBCK still pulses once per line, but the last SUBCK in the field has an additional SUBCK pulse, whose location is determined by the SUBCKHP_TOG registers, as shown in Figure 82. Finer resolution of the exposure time is possible using this mode.
AD9920A VD HD VSG tEXP tEXP SUBCK PROGRAMMABLE SETTINGS: 1. PULSE POLARITY USING THE SUBCK_POL REGISTER. 2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THIS EXAMPLE). 3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING THE SUBCK_TOG1 TOGGLE POSITION REGISTER. 06878-081 SUBCK Figure 81. Normal SUBCK Operation VD HD VSG tEXP tEXP NOTES 1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE. 2.
AD9920A FIELD COUNTERS The AD9920A contains three field counters (primary, secondary, and mode). When these counters are active, they increment with each VD cycle. The mode counter is the field counter used with the mode register to control the vertical timing signals (see the Mode Registers section). The primary and secondary counters are more flexible and are generally used for shuttering signal applications.
AD9920A 3. GENERAL-PURPOSE OUTPUTS (GPOs) The AD9920A provides programmable outputs to control a mechanical shutter, the strobe/flash, the CCD bias select signal, or any other external component with general-purpose (GP) signals. Eight GP signals, with up to four toggles each, are available to be programmed and assigned to special GPO pins. These pins are bidirectional and allow visibility (as an output) and external control (as an input) of HBLK, PBLK, CLPOB, and OUT_CONTROL.
AD9920A Register LUT_FOR_GP78 Length (Bits) 4 Range Logic setting GPx_TOGx_FD GPx_TOGx_LN GPx_TOGx_PX GPO_INT_EN 13 13 13 1 0 to 8191 fields 0 to 8191 lines 0 to 8191 pixels On/off Description Desired logic to be realized on GPO7 combined with GPO8. Example logic settings for LUT_FOR_GPxy: 0x06 = GPy XOR GPx (see Figure 89). 0x07 = GPy NAND GPx. 0x08 = GPy AND GPx. 0x0E = GPy OR GPx. Field of activity, relative to primary and secondary counter for corresponding toggle.
AD9920A Single-Field Toggles Scheduled Toggles Single-field toggles occur in the next field only. There can be up to four toggles in the field. The mode is set with GP_PROTOCOL equal to 1, and the toggles are triggered in the next field by writing to the MANUAL_TRIG register (Register 0x70, Bits[13:6]). In this mode, the field toggle settings must be set to a value of 1. Two consecutive fields do not have activity.
AD9920A RapidShot Sequences ShotTimer Sequences RapidShot technology provides continuous repetition of scheduled toggles. ShotTimer technology provides internal delay of scheduled toggles. The delay is in terms of fields. Preparation Preparation The GP toggle positions can be programmed any time prior to use. For example, The GP toggle positions can be programmed any time prior to use.
AD9920A GP LOOKUP TABLE (LUT) Table 46. LUT Results Based on GP1 and GP2 Values The AD9920A is equipped with a lookup table for each pair of consecutive GP signals when configured as outputs. GPO1 is always combined with GPO2, GPO3 is always combined with GPO4, GPO5 is always combined with GPO6, and GPO7 is always combined with GPO8. The external GPO outputs from each pair can output the result of the LUT or the original GP internal signal.
AD9920A Write to the mode registers to configure the next five fields. The first two fields during exposure are the same as the current draft mode fields, and the following three fields are the still image frame readout fields. The register settings for the draft mode field and the three readout fields are previously programmed. Note that if the mode registers are changed to VD updated, only one field of exposure should be included (the second one) because the mode settings are delayed an extra field.
Rev. B | Page 70 of 112 CCD OUT VSUB (GPO3) MECHANICAL SHUTTER MSHUT (GPO2) STROBE (GPO1) SUBCK VSG VD PRIMARY COUNT SERIAL WRITES DRAFT IMAGE 0 (IDLE) 1 2 3 tEXP 2 EXAMPLE 1 4 DRAFT IMAGE 1 CLOSED EXAMPLE 2 OPEN 5 6 3 STILL IMAGE FIRST FIELD 7 STILL IMAGE SECOND FIELD STILL IMAGE READOUT 4 8 5 9 STILL IMAGE THIRD FIELD 10 10 10 10 0 OPEN 0 DRAFT IMAGE AD9920A Figure 90.
AD9920A SG CONTROL USING GPO The AD9920A uses two of the GPO signals to generate the SG signals for the three-level outputs V5 and V6. Because GPO5 and GPO6 are used as inputs to the vertical driver, they must be properly initialized at power-up to avoid incorrect V-driver output levels. During different CCD timing modes, the GPO signals can be controlled in several ways to produce the proper SG signal operation.
AD9920A SERIAL WRITES 7 5 1 2 3 4 6 8 VD STILL IMAGE READOUT VSG (XSG1 TO XSG7) 8 GPO5 (XSG8 FOR V5) tEXP OPEN MECHANICAL SHUTTER OPEN CLOSED STILL IMAGE FIRST FIELD DRAFT IMAGE DRAFT IMAGE STILL IMAGE SECOND FIELD STILL IMAGE THIRD FIELD DRAFT IMAGE CCD OUT 06878-092 SUBCK Figure 92.
AD9920A MANUAL SHUTTER OPERATION USING ENHANCED SYNC MODES Shutter Operation in SLR Mode The AD9920A also supports an external signal to control exposure, using the SYNC input. Generally, the SYNC input is used as an asynchronous reset signal during master mode operation. When the enhanced SYNC mode is enabled, the SYNC input provides additional control of the exposure operation. 1. Normal SYNC Mode (Mode 1) 2. The following steps are shown in Figure 99.
AD9920A SYNC VD FIELD DESIGNATOR 7 3 5 SUSPEND HD NOTES 1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13). 4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT. 5. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUT_CONTROL = LOW. 6.
AD9920A SYNC 1 VD VDLEN 2 HD SCP 3 XV1 TO XV24 06878-096 1SYNC_MASK_VD REGISTER ENABLES MASKING OF VD DURING SYNCSUSPEND WHEN SET HIGH (DEFAULT). 2SYNC_MASK_HD REGISTER ENABLES MASKING OF HD DURING SYNCSUSPEND WHEN SET HIGH (DEFAULT). 3V-OUTPUT PULSES CONTINUE IN SEQUENCE. Figure 96. Enhanced SYNC Mode 3 SYNC VD 1 1VD 1 1 1 1 REGISTERS ARE UPDATED HERE. 06878-097 1 NOTES 1. VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) ARE DISABLED DURING THE SYNC INTERVAL. Figure 97.
AD9920A 4 SYNC 1 2 VD 3 FIELD DESIGNATOR 3 5 7 3 5 7 3 5 7 V-OUTPUTS MSHUT 5 DRAFT EXPOSURE 5 DUMMY FIELD READOUT ODD SHUTTER OPERATION IN SLR MODE 1REFER TO STEP 1. 2REFER TO STEP 2. 3REFER TO STEP 3. 4REFER TO STEP 4. 5SUBCK OUTPUT IS SUPPRESSED DURING EXPOSURE AND READOUT WHEN EXPOSURE TRIGGER IS USED. Figure 99. Enhanced SYNC Mode—Manual Shutter Operation, SLR Mode Rev.
AD9920A ANALOG FRONT END DESCRIPTION AND OPERATION 0.1µF 0.1µF AVDD REFB REFT 0.4V DC RESTORE 1.4V AD9920A FIXED DELAY CLI 0.5V SHP PBLK SHP SHD 6dB S11 0.
AD9920A Variable Gain Amplifier (VGA) The VGA stage provides a gain range of approximately 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. A gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared with 1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB. The VGA gain curve follows a linear-in-dB characteristic. The exact VGA gain is calculated for any gain register value by Gain (dB) = (0.0358 × Code) + 5.
AD9920A APPLICATIONS INFORMATION 7. POWER-UP SEQUENCE FOR MASTER MODE When the AD9920A is powered up, the following sequence is recommended (refer to Figure 102 for each step). Note that a SYNC signal is required for master mode operation. If an external SYNC pulse is not available, it is possible to generate an internal SYNC event by writing to the SWSYNC register. 1. 2. 3. 4. 5. 6. Turn on the 3 V and 1.8 V power supplies for the AD9920A and start master clock CLI.
AD9920A 4 1 VH SUPPLY +3V SUPPLIES +1.8V SUPPLY POWER 0V SUPPLIES VM SUPPLY VL SUPPLY CLI (INPUT) SERIAL WRITES 2 3 5 6 8 7 500µs 9 100µs 10 11 SYNC/RST 12 VD (INPUT) HD (INPUT) LOW BY DEFAULT XV1 TO XV24 XSUBCK (INTERNAL) H2, H4, H6, H8 HIGH-Z BY DEFAULT H-CLOCKS CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER UPDATED AT VD/HD EDGE H1, H3, H5, H7, RG VDD V1 TO V16 (V-DRIVER OUTPUT) V-DRIVER OUTPUTS ACTIVE VH WHEN VDR_EN IS HIGH VM 06878-102 VDR_EN 0V VL (SUBCK ONLY) Figure 102.
AD9920A 6. POWER-UP SEQUENCE FOR SLAVE MODE When the AD9920A is used in slave mode, the VD/HD inputs are used to synchronize the internal counters. For more detail on the counter reset operation, see Figure 103. 1. 2. 3. 4. 5. Turn on the 3 V and 1.8 V power supplies for the AD9920A, and start master clock CLI. Reset the internal AD9920A registers. If the SYNC/RST pin is functioning as RST, apply a rising edge to the SYNC/RST pin. If the SYNC/RST pin is functioning as SYNC, tie this pin high.
AD9920A 4 1 VH SUPPLY +3V SUPPLIES +1.8V SUPPLY POWER 0V SUPPLIES VM SUPPLY VL SUPPLY CLI (INPUT) SERIAL WRITES 2 3 5 6 7 8 500µs 9 10 11 100µs SYNC/RST 12 VD (INPUT) HD (INPUT) LOW BY DEFAULT XV1 TO XV24 XSUBCK (INTERNAL) H2, H4, H6, H8 HIGH-Z BY DEFAULT CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER UPDATED AT VD/HD EDGE H1, H3, H5, H7, RG H-CLOCKS VDD V1 TO V16 (V-DRIVER OUTPUT) VH VM V-DRIVER OUTPUTS ACTIVE WHEN VDR_EN IS HIGH 06878-103 VDR_EN 0V VL (SUBCK ONLY) Figure 103.
AD9920A 3. POWER-DOWN SEQUENCE FOR MASTER AND SLAVE MODES 2. 4. 5. Write 0 to the appropriate bit in the GPO_OUTPUT_EN register (Address 0x7A) to set the appropriate VDR_EN control signal low. The next VD edge updates Address 0x7A, causing the VDR_EN signal to go low and disabling the V-driver outputs. If operating in slave mode, turn off VD and HD after VDR_EN switches low. 4 VH SUPPLY 5 +3V SUPPLIES +1.
AD9920A • ADDITIONAL RESTRICTIONS IN SLAVE MODE When operating in slave mode, note the following restrictions: • VD tVDHD HD tHDCLI tCONV CLI tCLISHP tCLIDLY SHPLOC INTERNAL tSHPINH SHDLOC INTERNAL HD INTERNAL H-COUNTER RESET 35.5 CYCLES H-COUNTER (PIXEL COUNTER) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 2 NOTES: 1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED BY SHPLOC (INTERNAL SAMPLING EDGE). 2.
AD9920A VERTICAL TOGGLE POSITION PLACEMENT NEAR COUNTER RESET An additional consideration during the reset of the internal counters is the vertical toggle position placement. There is a region of 36 pixels prior to the internal counter reset in which no toggles can take place. Figure 107 shows this restriction for slave mode. The last 36 pixels before the counters are reset cannot be used.
AD9920A STANDBY MODE OPERATION The AD9920A contains three standby modes to optimize the overall power dissipation in a particular application. Bits[1:0] of Address 0x00 control the power-down state of the device. The vertical outputs can also be programmed to hold a specific value during the Standby3 mode by using Address 0x26. This register is useful during power-up if different polarities are required by the V-driver and CCD to prevent damage when VH and VL areas are applied.
AD9920A Table 50.
AD9920A CIRCUIT LAYOUT INFORMATION The PCB layout is critical in achieving good image quality from the AD9920A. All of the supply pins, particularly the AVDD, TCVDD, RGVDD, and HVDD pins, must be decoupled to ground with good quality, high frequency chip capacitors. The decoupling capacitors should be located as close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. If possible, there should be a 4.
AD9920A CIRCUIT CONFIGURATIONS SERIAL INTERFACE (FROM ASIC/DSP) 3 6 GENERAL-PURPOSE OUTPUTS NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11) OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) HORIZONTAL SYNC IN/OUT VERTICAL SYNC IN/OUT MASTER CLOCK INPUT (3V LOGIC) 0.1µF EXTERNAL RESET IN (TIE TO IOVDD IF RESET IS NOT USED) DCLK OUTPUT DATA OUTPUTS 0.1µF 12 0.
AD9920A SERIAL INTERFACE (FROM ASIC/DSP) 3 6 GENERAL-PURPOSE OUTPUTS NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11) OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) HORIZONTAL SYNC IN/OUT VERTICAL SYNC IN/OUT MASTER CLOCK INPUT (3V LOGIC) EXTERNAL RESET IN (TIE TO IOVDD IF RESET IS NOT USED) DCLK OUTPUT DATA OUTPUTS 0.1µF 12 0.1µF 0.
AD9920A SERIAL INTERFACE (FROM ASIC/DSP) 3 6 GENERAL-PURPOSE OUTPUTS NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11) OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) HORIZONTAL SYNC IN/OUT VERTICAL SYNC IN/OUT MASTER CLOCK INPUT (3V LOGIC) 0.1µF EXTERNAL RESET IN (TIE TO IOVDD IF RESET IS NOT USED) DCLK OUTPUT DATA OUTPUTS 0.1µF 12 0.
AD9920A SERIAL INTERFACE (FROM ASIC/DSP) 3 6 GENERAL-PURPOSE OUTPUTS NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11) OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) HORIZONTAL SYNC IN/OUT VERTICAL SYNC IN/OUT MASTER CLOCK INPUT (3V LOGIC) EXTERNAL RESET IN (TIE TO IOVDD IF RESET IS NOT USED) DCLK OUTPUT DATA OUTPUTS 0.1µF 12 0.1µF 0.
AD9920A SERIAL INTERFACE Figure 114 shows a more efficient way to write to the registers, using the AD9920A address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 28-bit data-words. Each new 28-bit data-word is automatically written to the next highest register address. By eliminating the need to write each 12-bit address, faster register loading is achieved. Continuous write operations can be used starting with any register location.
AD9920A LAYOUT OF INTERNAL REGISTERS The AD9920A address space is divided into two register areas, as illustrated in Figure 115. In the first address space, Address 0x00 to Address 0xFF contain the registers for the AFE, miscellaneous, VD/HD, I/O and CP, timing core, shutter and GPO, and update control functions. The second address space, beginning at Address 0x400, consists of the V-pattern groups, V-sequences, and field registers.
AD9920A delays the VD-updated register updates to any HD line in the field. Note that the field registers are not affected by the update register. UPDATING NEW REGISTER VALUES The AD9920A internal registers are updated at different times, depending on the particular register. Table 51 summarizes the four register update types: SCK, VD, SG line, and SCP. Tables in the Complete Register Listing section contain an update type column that identifies when each register is updated.
AD9920A COMPLETE REGISTER LISTING When an address contains fewer than 28 data bits, all remaining bits must be written as 0s. Table 52.
AD9920A Table 53.
AD9920A Table 54. VD/HD Registers Address 0x20 0x21 0x22 Data Bits [0] [0] [12:0] [25:13] Default Value 0 0 0 0 Default Update Type SCK VD VD Name MASTER VDHDPOL HDRISE VDRISE Description VD/HD master or slave mode. 0 = slave mode, 1 = master mode. VD/HD active polarity. 0 = low, 1 = high. Rising edge location for HD. Minimum value is 36 pixels. Rising edge location for VD. Table 55.
AD9920A Address 0x2C 0x2D 0x2E 0x2F Data Bits [4:0] [9:5] [27] [27] [27] Default Value 0 0 0 0 0 Update Type SCK SCK SCK SCK Name FIELD6 FIELD7 UNUSED UNUSED UNUSED Description Selected sixth field in the mode register. Selected seventh field in the mode register. Do not access, or set to 0. Do not access, or set to 0. Do not access, or set to 0. Table 57.
AD9920A Address 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Data Bits [2:0] Default Value 0x01 Update Type SCK [6:4] [10:8] [14:12] [18:16] 0x1 0x1 0x1 0x1 [22:20] [2:0] [6:4] [10:8] [14:12] [18:16] [22:20] [5:0] [13:8] [21:16] [5:0] [13:8] 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0 0x20 0x10 0 0x20 [16] 0 DCLKMODE [18:17] [19] 0 0 Test DCLKINV [22:20] [27] [27] [27] [27] [27] [27] 0 0 0 0 0 0 0 Name H1DRV H2DRV H3DRV H4DRV HLDRV SCK SCK SCK SCK SCK SCK SCK SCK SCK RGDRV H5DRV H6DRV H7DRV
AD9920A Table 59.
AD9920A Address 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 Data Bits [0] [1] [2] [3] [4] [5] [6] [7] [8] Default Value 0 0 0 0 0 0 0 0 0x01 Update Type VD [9] 0x01 SEL_GP2 [10] 0x01 SEL_GP3 [11] [12] [13] [14] [15] [23:16] [24] 0x01 0x01 0x01 0x01 0x01 0 0 SEL_GP4 SEL_GP5 SEL_GP6 SEL_GP7 SEL_GP8 GPO_OUTPUT_EN GPO5_OVERRIDE [25] 0 GPO6_OVERRIDE [26] 0 GPO7_OVERRIDE [27] 0 GPO8_OVERRIDE [7:0] 0 [11:8] [15:12] [19:16] [23:20] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [1
AD9920A Address 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D Data Bits [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13]
AD9920A Address 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF Data Bits [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [7:0] [27] [27] [27] Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Update Type VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD Name GP6_TOG3_PX
AD9920A Address 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF Data Bits [27:0] [27:0] [27:0] [27:0] [27:0] [27:0] Default Value 0 0 0 0 0 0 Update Type Name UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED Description Do not access, or write to 0x00. Do not access, or write to 0x00. Do not access, or write to 0x00. Do not access, or write to 0x00. Do not access, or write to 0x00. Do not access, or write to 0x00. Table 61.
AD9920A Address 0xDE 0xDF Data Bits [27:0] [27:0] Default Value 0 0 Update SCK SCK Name Test Test Description Test use only. Set to 0. Test use only. Set to 0. Table 62.
AD9920A Address 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Data Bits [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13]
AD9920A Table 63.
AD9920A Data Bits [23:0] Default Value X Update Type SCP 0x09 [4:0] [9:5] [14:10] [19:15] [20] [21] X X X X X X SCP VPATSELA VPATSELB VPATSELC VPATSELD SEQ_ALT_INC SEQ_ALT_RST 0x0A [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [20:13] [21] [22] [23] [24] [12:0] [25:13] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
AD9920A Address 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 Data Bits [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [25:13] [12:0] [16:13] [20:17] [2:0] [6:4] [10:8] [14:12] [18:16] [22:20] [12:0] [25:13] [12:0] [25:13] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [12:0] Default Value X X X X X X X X X X X X X [13] X X X X X X X X X X X X X X X X X X Update Type SCP SCP SCP SCP SCP SCP SCP SCP SCP SCP SCP SCP SCP SCP Name HBLKTOGO3 HBL
AD9920A Table 64.
AD9920A OUTLINE DIMENSIONS A1 BALL CORNER 8.10 8.00 SQ 7.90 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G BALL A1 PAD CORNER 6.50 BSC SQ H J K L 0.65 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 1.31 1.16 0.91 MIN 0.25 MIN 0.45 0.40 0.35 BALL DIAMETER COPLANARITY 0.10 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. 080807-A *1.40 Figure 118.
