Datasheet

AD9913
Rev. A | Page 9 of 32
–
50
–90
0 250
07002-033
SYSTEM CLOCK (MHz)
SFDR (dBc)
–55
–60
–65
–70
–75
–80
–85
50 100 150 200
39.88%
26.58%
10.21%
Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)
–
100
–170
10 100M
07002-042
FREQUENCY (MHz)
PHASE NOISE (dBc/Hz)
–110
–120
–130
–140
–150
–160
100 1k 10k 100k 1M 10M
92.3MHz
48.9MHz
23.1MHz
6.1MHz
Figure 11. Residual Phase Noise vs. f
OUT
(PLL Bypassed)
−150
−50
100 100M
FREQUENCY (MHz)
PHASE NOISE (dBc/Hz)
1k 10k 100k 1M 10M
−60
−70
−80
−90
−100
−110
−120
−130
−140
99MHz
12.5MHz
49MHz
25MHz
07002-012
Figure 12. Absolute Phase Noise vs. f
OUT
Using the Internal PLL
(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)
–
50
–90
00
07002-034
f
OUT
(% of System Clock)
SFDR (dBc)
.45
–55
–60
–65
–70
–75
–80
–85
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
REFSPUR
PLL ×10
BYPASS
Figure 13. SFDR Without the Internal PLL
(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)