Datasheet

AD9913
Rev. A | Page 30 of 32
Control Function Register 2 (CFR2)
Address 0x01; 2 bytes are assigned to this register.
Table 11. Bit Descriptions for CFR2
Bit(s) Bit Name Description
15 PLL Output Div by 2 See Table 7 for details on multiplication factor configuration.
14:9 PLL Multiplication Factor
8 Open Leave this bit at the default state.
7 CMOS Clock Mode See Table 6 for directions on programming this bit.
6 Crystal Clock Mode See Table 6 for directions on programming this bit.
5 PLL Power-Down
0 = PLL is active
1 = PLL is inactive and in its lowest power state
4 PLL LO Range 0 = use this setting for PLL if the PLL reference frequency is >5 MHz.
1 = use this setting for PLL if the PLL reference frequency is <5 MHz.
3 PLL Input Div by 2 0 = the PLL reference frequency = the REF_CLK input frequency.
1 = the PLL reference frequency = ½ the REF_CLK input frequency.
2 VCO2 Sel
0 = use this setting for VCO frequencies below 100 MHz and/or to optimize for power rather
than performance.
1 = use this setting to optimize for performance; this setting results in slightly higher power
consumption. Note: When setting this bit, an IO_UPDATE must occur within 40 μs of the PLL
power-down bit (CFR2 [5]) going low.
1 PLL Reset 0 = the PLL logic is reset and non-operational until this bit is set.
1 = the PLL logic operates normally.
0 PLL Lock This read-only bit is set when the REF_CLK PLL is locked.
DAC Control Register
Address 0x02; 4 bytes are assigned to this register.
Table 12. Bit Descriptions for DAC Control Register
Bit(s) Bit Name Description
15:14, 10 Open Leave these bits at their default state.
9:0 FSC This 10-bit number controls the full-scale output current of the DAC.
31:16,13:11 Reserved Leave these bits at their default state.
Frequency Tuning Word Register (FTW)
Address 0x03, 4 bytes are assigned to this register.
Table 13. Bit Descriptions for FTW Register
Bit(s) Bit Name Description
31:0 Frequency Tuning Word 32-bit frequency tuning word.
Phase Offset Word Register (POW)
Address 0x04, 2 bytes are assigned to this register.
Table 14. Bit Descriptions for POW Register
Bit(s) Bit Name Description
15:14 Open Leave these bits at their default state.
13:0 Phase Offset Word 14-bit phase offset word.