Datasheet

AD9913
Rev. A | Page 29 of 32
Bit(s) Bit Name Description
13:12 Destination
00 = In direct switch mode, use this setting for FSK.
In linear sweep mode, the auxiliary accumulator is used for frequency sweeping.
In programmable modulus mode, these bits must be 00.
01 = In direct switch mode, use this setting for PSK.
In linear sweep mode, the auxiliary accumulator is used for phase sweeping.
11 Auxiliary Accumulator Enable 0 = auxiliary accumulator is inactive.
1 = auxiliary accumulator is active.
10 DC Output Active This bit is ignored if linear sweep is disabled (see CFR1 [11]).
0 = normal operating state.
1 = the output of the DAC is driven to full-scale and the DDS output is disabled.
9
Linear Sweep State Trigger
Active
0 = edge triggered mode active.
1 = state triggered mode active.
8 Linear Sweep No-Dwell Active This bit is ignored if linear sweep is disabled (see CFR1[11]).
0 = when a sweep is completed, the device holds at the final state.
1 = when a sweep is completed, the device reverts to the initial state.
7 External Power-Down Mode
0 = the external power-down mode selected is the fast recovery power-down mode. In this
mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital
logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are
not powered down.
1 = the external power-down mode selected is the full power-down mode. In this mode,
when the PWR_DWN_CTL pin is high, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to power up.
6 Digital Power-Down 0 = the digital core is enabled for operation.
1 = the digital core is disabled and is in a low power dissipation state.
5 DAC Power-Down 0 = the DAC is enabled for operation.
1 = the DAC is disabled and is in its lowest power dissipation state.
4 Clock Input Power-Down 0 = normal operation.
1 = shut down all clock generation including the system clock signal going into the digital
section.
3 LOAD SRR @ IO_UPDATE
0 = every time the linear sweep rate register is updated, the ramp rate timer keeps its
operation until it times out and then loads the update value into the timer.
1 = the timer is interrupted immediately upon the assertion of IO_UPDATE and the value is
loaded.
2
Autoclear Auxiliary
Accumulator
0 = normal operation.
1 = the auxiliary accumulator is synchronously cleared (zero is loaded) for one cycle upon
receipt of the IO_UPDATE sequence indicator.
1 Autoclear Phase Accumulator
0 = normal operation.
1 = the phase accumulator is synchronously cleared for one cycle upon receipt of the
IO_UPDATE sequence indicator.
0 Enable Sine Output 0 = the angle-to-amplitude conversion logic employs a cosine function.
1 = the angle-to-amplitude conversion logic employs a sine function.