Datasheet

AD9913
Rev. A | Page 24 of 32
1.
The user supplies the PCLK,
CS
, R/
W
, and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
Data Read Operation
A typical read operation follows the steps shown in Figure 33.
1.
The user supplies PCLK,
CS
, R/
W
, and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
2.
CS
, R/
W
, and the address lines must meet the set up and
hold times relative to the 1
st
PCLK rising edge.
3.
Data lines must meet the set up and hold times relative to
the 2
nd
PCLK rising edge.
2.
CS
, R/
W
, and the address lines must meet the setup and
hold times relative to the 1
st
PCLK rising edge.
4.
CS
must meet the set up and hold times relative to the 3
rd
PCK rising edge.
3.
The user releases the bus to read.
4.
The AD9913 drives data onto the bus after the second
PCLK rising edge.
5.
The IO_UPDATE is not shown in Figure 34. The
IO_UPDATE transfers the contents from a write sequence
to the active register. See the Register Update (I/O Update)
section.
5.
CS
must meet the set up and hold times to the 3
rd
PCLK
rising edge.
Data Write Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
PCLK
READ OPERATION
ADDR0 DATA0 DATA1ADDR1
CS
R/W
ADDR/DATA
0.3ns
t
CHD
t
CSU
t
DVLD
t
AHD
t
ASU
3ns 0.3ns 8ns 3ns
07002-028
Figure 33. Parallel Port Read Timing
PCLK
WRITE OPERATION
ADDR/DATA
CS
R/W
DATA1ADDR1DATA0ADDR0
0.3ns
t
CHD
0.3ns
t
DHD
3ns
t
DSU
3ns
t
ASU
0.3ns
t
AHD
3ns
t
CSU
07002-029
Figure 34. Parallel Port Write Timing