Datasheet

AD9913
Rev. A | Page 12 of 32
THEORY OF OPERATION
DDS CORE
The DDS block generates a reference signal (sine or cosine
based on the selected DDS sine output bit). The parameters of
the reference signal (frequency and phase), are applied to the
DDS at its frequency and phase offset control inputs, as shown
in Figure 19.
07002-030
SYSTEM
CLOCK
32
15
FREQUENCY
CONTROL
ANGLE
TO
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
PHASE
OFFSET
CONTROL
TO DAC
MSBs
DQ
R
ACCUMULATOR
RESET
32
MSB ALIGNED
DDS SIGNAL CONTROL PARAMETERS
10
15
32
32
14
32-BIT
ACCUMULATOR
Figure 19. DDS Block Diagram
The output frequency (f
OUT
) of the AD9913 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. In all modes except for programmable modulus, the
relationship between f
OUT
, FTW, and f
SYSCLK
is:
SYSCLK
OUT
f
FTW
f
⎟
⎠
⎞
⎜
⎝
⎛
=
32
2
(1)
where
FTW is a 32-bit integer ranging in value from 0 to
2,147,483,647 (2
31
− 1), which represents the lower half of the
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, ½ f
SYSCLK
).
The FTW required to generate a desired value of
f
OUT
is found
by solving Equation 1 for FTW as given in Equation 2
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
SYSCLK
OUT
f
f
FTW
32
2round (2)
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value.
For applications where rounding to the nearest available fre-
quency is not acceptable, programmable modulus mode enables
additional options.
The relative phase of the DDS signal can be digitally controlled
by means of a 14-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
⎟
⎠
⎞
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛
π
=θΔ
14
14
2
360
2
2
POW
POW
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the
POW value necessary to develop an arbitrary Δθ, solve the
above equation for POW and round the result (in a manner
similar to that described for finding an arbitrary FTW in
Equation 1 and Equation 2).
FTW POW
1
0
EXTERNAL
INTERNAL
REGISTER MAP AND TIMING CONTROL
+
DAC
IOUT
IOUT
RSET
DDS CORE
I/O PORT
CLOCK PORT
REF_CLK
REF_CLK
PLL
MULTIPLIER
CLOCK
SELECTION
SER/PAR
CS
SCLK/PCLK
AD[7:0]/PS[2:0]
MASTER RESET
PWR_DWN_CTL
IO_UPDATE
SYNC_CLK
1 0 1 0
PROFILE
SELECTIONS
1
0
1
0
Z
–1
AUXILIARY
ACCUMULATOR
ANGLE TO
AMPLITUDE
PHASE
ACCUMULATOR
PHASE
OFFSET
07002-015
SDIO (WR/RD)
32 32
32
32
32 14
14
10
2
Figure 20. Detailed Block Diagram