Inc. Recording Equipment User Manual
Table Of Contents
- Features
- Applications
- General Description
- Basic Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Input/Output Termination Recommendations
- Theory of Operation
- Thermal Performance
- Power-Up
- Power Supply Partitioning
- Serial Control Port
- I/O Register Map
- I/O Register Descriptions
- Serial Port Configuration (Register 0x0000 to Register 0x0005)
- Power-Down and Reset (Register 0x0010 to Register 0x0013)
- System Clock (Register 0x0020 to Register 0x0022)
- CMOS Output Divider (S-Divider) (Register 0x0100 to Register 0x0106)
- Frequency Tuning Word (Register 0x01A0 to Register 0x01AD)
- Register 0x01A0 to Register 0x01A5—Reserved
- Register 0x01A6—FTW0 (Frequency Tuning Word)
- Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AC—Phase
- Register 0x01AD—Phase (Continued)
- Doubler and Output Drivers (Register 0x0200 to Register 0x0201)
- Calibration (User-Accessible Trim) (Register 0x0400 to Register 0x0410)
- Harmonic Spur Reduction (Register 0x0500 to Register 0x0509)
- Outline Dimensions
AD9912
Rev. D | Page 3 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVSS = 0 V, DVSS = 0 V, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O (Pin 1) 3.135 3.30 3.465 V
DVDD (Pin 3, Pin 5, Pin 7) 1.71 1.80 1.89 V
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49) 3.135 3.30 3.465 V
AVDD3 (Pin 37) 1.71 3.30 3.465 V Pin 37 is typically 3.3 V but can be set to 1.8 V
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
1.71 1.80 1.89 V
SUPPLY CURRENT See also the Total Power Dissipation
specifications
I
AVDD3
(Pin 37) 8 9.6 mA CMOS output driver at 3.3 V, 50 MHz, with
5 pF load
I
AVDD3
(Pin 46, Pin 47, Pin 49) 26 31 mA DAC output current source, f
S
= 1 GSPS
I
AVDD
(Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45)
113 136 mA Aggregate analog supply, with system
clock PLL, HSTL output driver, and S-divider
enabled
I
AVDD
(Pin 53) 40 48 mA DAC power supply
I
DVDD
(Pin 3, Pin 5, Pin 7) 205 246 mA Digital core (SpurKiller off)
I
DVDD_I/O
(Pin 1, Pin 14
1
) 2 3 mA Digital I/O (varies dynamically)
LOGIC INPUTS (Except Pin 32) Pin 9, Pin 10, Pin 54, Pin 55, Pin 58 to Pin 61,
Pin 63, Pin 64
Input High Voltage (V
IH
) 2.0 DVDD_I/O V
Input Low Voltage (V
IL
) DVSS 0.8 V
Input Current (I
INH
, I
INL
) ±60 ±200 µA At V
IN
= 0 V and V
IN
= DVDD_I/O
Maximum Input Capacitance (C
IN
) 3 pF
CLKMODESEL (Pin 32) LOGIC INPUT Pin 32 only
Input High Voltage (V
IH
) 1.4 AVDD V
Input Low Voltage (V
IL
) AVSS 0.4 V
Input Current (I
INH
, I
INL
) −18 −50 µA At V
IN
= 0 V and V
IN
= AVDD
Maximum Input Capacitance (C
IN
) 3 pF
LOGIC OUTPUTS Pin 62 and the following bidirectional pins:
Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
Output High Voltage (V
OH
) 2.7 DVDD_I/O V I
OH
= 1 mA
Output Low Voltage (V
OL
) DVSS 0.4 V I
OL
= 1 mA
FDBK_IN INPUT Pin 40, Pin 41
Input Capacitance 3 pF
Input Resistance 18 22 26 kΩ Differential
Differential Input Voltage Swing 225 mV p-p Equivalent to 112.5 mV swing on each leg;
must be ac-coupled