Inc. Recording Equipment User Manual
Table Of Contents
- Features
- Applications
- General Description
- Basic Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Input/Output Termination Recommendations
- Theory of Operation
- Thermal Performance
- Power-Up
- Power Supply Partitioning
- Serial Control Port
- I/O Register Map
- I/O Register Descriptions
- Serial Port Configuration (Register 0x0000 to Register 0x0005)
- Power-Down and Reset (Register 0x0010 to Register 0x0013)
- System Clock (Register 0x0020 to Register 0x0022)
- CMOS Output Divider (S-Divider) (Register 0x0100 to Register 0x0106)
- Frequency Tuning Word (Register 0x01A0 to Register 0x01AD)
- Register 0x01A0 to Register 0x01A5—Reserved
- Register 0x01A6—FTW0 (Frequency Tuning Word)
- Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AC—Phase
- Register 0x01AD—Phase (Continued)
- Doubler and Output Drivers (Register 0x0200 to Register 0x0201)
- Calibration (User-Accessible Trim) (Register 0x0400 to Register 0x0410)
- Harmonic Spur Reduction (Register 0x0500 to Register 0x0509)
- Outline Dimensions

AD9912
Rev. D | Page 10 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, AVDD3, and DVDD at nominal supply voltage; DAC R
SET
= 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference
phase noise used for generating these plots.
06763-003
0 100 200 300 400 500
OUTPUT FREQUENCY (MHz)
–50
–55
–60
–65
–70
–75
–80
SFDR (dBc)
+25°C
–40°C
+85°C
Figure 3. Wideband SFDR vs. Output Frequency at −40°C, +25°C, and +85°C,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06763-004
0 100 200 300 400 500
OUTPUT FREQUENCY (MHz)
–50
–55
–60
–65
–70
–75
–80
SFDR (dBc)
HIGH V
DD
NORMAL V
DD
LOW V
DD
Figure 4. Variation of Wideband SFDR vs. Frequency over DAC Power Supply
Voltage, SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06763-005
0 100 200 300 400 500
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SIGNAL POWER (dBm)
20.1MHz
–79dBc
500MHz
3kHz
10kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 5. Wideband SFDR at 20.1 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06763-006
0 100 200 300 400 500
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SIGNAL POWER (dBm)
98.6MHz
–67dBc
500MHz
3kHz
10kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 6. Wideband SFDR at 98.6 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06763-007
0 100 200 300 400 500
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SIGNAL POWER (dBm)
201.1MHz
–61dBc
500MHz
3kHz
10kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 7. Wideband SFDR at 201.1 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06763-008
0 100 200 300 400 500
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SIGNAL POWER (dBm)
398.7MHz
–59dBc
500MHz
3kHz
10kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 8. Wideband SFDR at 398.7 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)