Datasheet
AD9911
Rev. 0 | Page 10 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1
SYNC_IN
2
SYNC_OUT
3
MASTER_RESET
4
PWR_DWN_CTL
5
AVDD
6
NC
7
AVDD
8
AVDD
9
AVDD
10
NC
11
AVDD
12
NC
13
AVDD
14
AVDD
35
IOUT
36
IOUT
37
AVDD
38
AGND
39
AVDD
40
P0
41
P1
42
P2
34
AGND
33
AVDD
32
NC
31
AVDD
30
AVDD
29
AVDD
15
AV
DD
16
NC
17
DAC_RSET
19
AVDD
21
AVDD
20
AGND
22
REF_CLK
23
REF_C
LK
24
CLK_MODE_SEL
25
AGND
26
AVDD
27
LOOP_FILTER
28
NC
18
AGND
45
DVDD
46
I/O_UPDATE
47
CS
48
SCLK
49
DVDD_I/O
50
SDIO
_0
51
SDIO_1
52
SDIO_2
53
SDIO_3
54
SYNC_CL
K
44
DGND
43
P3
TOP VIEW
(Not to Scale)
AD9911
55
DVDD
56
DGND
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
05785-006
Figure 6. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic I/O Description
1 SYNC_IN I
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_OUT pin of the master
AD9911 device.
2 SYNC_OUT O
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_IN pin of the slave
AD9911 device.
3 MASTER_RESET I
Active High Reset Pin. Asserting this pin forces the internal registers to the default
state shown in the
Register Map section.
4 PWR_DWN_CTL I External Power-Down Control. See the Power Down Functions section for details.
5, 7, 8, 9, 11, 13, 14,
15, 19, 21, 26, 29,
30, 31, 33, 37, 39
AVDD I Analog Power Supply Pins (1.8 V).
18, 20, 25, 34, 38 AGND I Analog Ground Pins.
45, 55 DVDD I Digital Power Supply Pins (1.8 V).
44, 56 DGND I Digital Power Ground Pins.
35
IOUT
O Complementary DAC Output. Terminates into AVDD.
36 IOUT O True DAC Output. Terminates into AVDD.
17 DAC_RSET I
Establishes the Reference Current for the DAC. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
22
REF_CLK
I
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in
single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
23 REF_CLK I
Reference Clock/Oscillator Input. When the REF_CLK operates in single-ended mode,
Pin 23 is the input. See the
Modes of Operation section for the reference clock
configuration.
24 CLK_MODE_SEL I
Control Pin for the Oscillator. CAUTION: Do not drive this pin beyond 1.8 V. When high
(1.8 V), the oscillator is enabled to accept a crystal as the REF_CLK source. When low,
the oscillator is bypassed.
27 LOOP_FILTER I
Connects to the External Zero Compensation Network of the PLL Loop Filter. Typically,
the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.