Datasheet

AD9910 Data Sheet
Rev. D | Page 8 of 64
Parameter Conditions/Comments Min Typ Max Unit
CMOS LOGIC INPUTS
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 90 150 µA
Logic 0 Current
90
150
µA
Input Capacitance 2 pF
XTAL_SEL INPUT
Logic 1 Voltage 1.25 V
Logic 0 Voltage 0.6 V
Input Capacitance 2 pF
CMOS LOGIC OUTPUTS
1 mA load
Logic 1 Voltage 2.8 V
Logic 0 Voltage 0.4 V
POWER SUPPLY CURRENT
I
AVDD
(1.8 V) 110 mA
I
AVDD
(3.3 V) 29 mA
I
DVDD
(1.8 V) 222 mA
I
DVDD
(3.3 V) 11 mA
TOTAL POWER CONSUMPTION
Single Tone Mode 715 950 mW
Rapid Power-Down Mode 330 450 mW
Full Sleep Mode
19
40
mW
1
The gain value for VCO range Setting 5 is measured at 1000 MHz.
2
Wake-up time refers to the recovery time from a power-down state. The longest time required is for the reference clock multiplier PLL to relock to the reference. The
wake-up time assumes that the recommended PLL loop filter values are used.
3
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.