Datasheet

Data Sheet AD9910
Rev. D | Page 7 of 64
Parameter Conditions/Comments Min Typ Max Unit
201.1 MHz Analog Output ±500 kHz –87 dBc
±125 kHz –87 dBc
±12.5 kHz –91 dBc
301.1 MHz Analog Output ±500 kHz –86 dBc
±125 kHz
–86
dBc
±12.5 kHz –88 dBc
401.3 MHz Analog Output ±500 kHz –84 dBc
±125 kHz –84 dBc
±12.5 kHz –85 dBc
SERIAL PORT TIMING CHARACTERISTICS
Maximum SCLK Frequency 70 Mbps
Minimum SCLK Clock Pulse Width Low 4 ns
High 4 ns
Maximum SCLK Rise/Fall Time
2
ns
Minimum Data Setup Time to SCLK 5 ns
Minimum Data Hold Time to SCLK 0 ns
Maximum Data Valid Time in Read Mode 11 ns
I/O_UPDATE/PROFILE[2:0] TIMING
CHARACTERISTICS
Minimum Setup Time to SYNC_CLK
1.75
ns
Minimum Hold Time to SYNC_CLK
0
ns
I/O_UPDATE Pulse Width
High
>1
SYNC_CLK cycle
Minimum Profile Toggle Period
2
SYNC_CLK cycles
TxENABLE and 16-BIT PARALLEL (DATA) BUS TIMING
Maximum PDCLK Frequency 250 MHz
TxENABLE/Data Setup Time (to PDCLK) 1.75 ns
TxENABLE/Data Hold Time (to PDCLK) 0 ns
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time
2
Fast Recovery
8
SYSCLK cycles
3
Full Sleep Mode
REFCLK multiplier enabled
1
ms
REFCLK multiplier disabled
150
μs
Minimum Reset Pulse Width High 5 SYSCLK cycles
3
DATA LATENCY (PIPELINE DELAY)
Data Latency, Single Tone or Using Profiles
Frequency, Phase, Amplitude-to-DAC Output Matched latency enabled and OSK
enabled
91 SYSCLK cycles
3
Frequency, Phase-to-DAC Output Matched latency enabled and OSK
disabled
79 SYSCLK cycles
3
Matched latency disabled 79 SYSCLK cycles
3
Amplitude-to-DAC Output Matched latency disabled 47 SYSCLK cycles
3
Data Latency Using RAM Mode
Frequency, Phase-to-DAC Output Matched latency enabled/disabled 94 SYSCLK cycles
3
Amplitude-to-DAC Output Matched latency enabled 106 SYSCLK cycles
3
Matched latency disabled 58 SYSCLK cycles
3
Data Latency, Sweep Mode
Frequency, Phase-to-DAC Output
Matched latency enabled/disabled
91
SYSCLK cycles
3
Amplitude-to-DAC Output Matched latency enabled 91 SYSCLK cycles
3
Matched latency disabled 47 SYSCLK cycles
3
Data Latency, 16-Bit Input Modulation Mode
Frequency, Phase-to-DAC Output Matched latency enabled 103 SYSCLK cycles
3
Matched latency disabled 91 SYSCLK cycles
3