Datasheet

AD9910 Data Sheet
Rev. D | Page 60 of 64
Multichip Sync Register—Address 0x0A
Four bytes are assigned to this register.
Table 26. Multichip Sync Register
Bit(s) Mnemonic Description
31:28 Sync validation delay This 4-bit number sets the timing skew (in ~75ps increments) between SYSCLK and the
delayed SYNC_INx signal for the sync validation block in the sync receiver. Default is 0000b.
27 Sync receiver enable 0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
26 Sync generator enable 0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
25
Sync generator polarity
0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
24 Open
23:18 Sync state preset value This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 000000b.
17:16 Open
15:11
Output sync generator
delay
This 5-bit number sets the output delay (in ~75 ps increments) of the sync generator.
Default is 00000b.
10:8 Open
7:3 Input sync receiver delay This 5-bit number sets the input delay (in ~75 ps increments) of the sync receiver. Default is
00000b.
2:0 Open
Digital Ramp Limit Register—Address 0x0B
Eight bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.
Table 27. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
Mnemonic
Description
63:32 Digital ramp upper limit 32-bit digital ramp upper limit value.
31:0 Digital ramp lower limit 32-bit digital ramp lower limit value.
Digital Ramp Step Size Register—Address 0x0C
Eight bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.
Table 28. Bit Descriptions for Digital Ramp Step Size Register
Bit(s) Mnemonic Description
63:32 Digital ramp decrement
step size
32-bit digital ramp decrement step size value.
31:0 Digital ramp increment
step size
32-bit digital ramp increment step size value.
Digital Ramp Rate Register—Address 0x0D
Four bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.
Table 29. Bit Descriptions for Digital Ramp Rate Register
Bit(s) Mnemonic Description
31:16 Digital ramp negative slope
rate
16-bit digital ramp negative slope value that defines the time interval between decrement
values.
15:0 Digital ramp positive slope
rate
16-bit digital ramp positive slope value that defines the time interval between increment
values.