Datasheet

Data Sheet AD9910
Rev. D | Page 59 of 64
I/O Update Rate Register—Address 0x04
Four bytes are assigned to this register. This register is effective without the need for an I/O update.
Table 22. Bit Descriptions for I/O Update Rate Register
Bit(s) Mnemonic Description
31:0 I/O update rate Ineffective unless CFR2[23] = 1. This 32-bit number controls the automatic I/O update
rate (see the Automatic I/O Update section for details); default is 0xFFFFFFFF.
Frequency Tuning Word Register (FTW)—Address 0x07
Four bytes are assigned to this register.
Table 23. Bit Descriptions for FTW Register
Bit(s) Mnemonic Description
31:0 Frequency tuning word 32-bit frequency tuning word.
Phase Offset Word Register (POW)—Address 0x08
Two bytes are assigned to this register.
Table 24. Bit Descriptions for POW Register
Bit(s) Mnemonic Description
15:0 Phase offset word 16-bit phase offset word.
Amplitude Scale Factor Register (ASF)—Address 0x09
Four bytes are assigned to this register.
Table 25. Bit Descriptions for ASF Register
Bit(s) Mnemonic Description
31:16 Amplitude ramp rate 16-bit amplitude ramp rate value. Effective only if CFR1[9:8] = 11b; see the Output Shift
Keying (OSK) section for details.
15:2 Amplitude scale factor 14-bit amplitude scale factor.
1:0 Amplitude step size Effective only if CFR1[9:8] = 11b; see the Output Shift Keying (OSK) section for details.