Datasheet

AD9910 Data Sheet
Rev. D | Page 58 of 64
Bit(s) Mnemonic Description
6 Data assembler hold last
value
Ineffective unless CFR2[4] = 1.
0 = the data assembler of the parallel data port internally forces zeros on the data path
and ignores the signals on the D[15:0] and F[1:0] pins while the TxENABLE pin is Logic 0
(default). This implies that the destination of the data at the parallel data port is
amplitude when TxENABLE is Logic 0.
1 = the data assembler of the parallel data port internally forces the last value received
on the D[15:0] and F[1:0] pins while the TxENABLE pin is Logic 1.
5 Sync timing validation
disable
0 = enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization
pulse sampling error.
1 = the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).
4 Parallel data port enable See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
3:0 FM gain See the Parallel Data Port Modulation Mode section for more details. Default is 0000b.
Control Function Register 3 (CFR3)—Address 0x02
Four bytes are assigned to this register.
Table 20. Bit Descriptions for CFR3
Bit(s) Mnemonic Description
31:30 Open
29:28 DRV0 Controls the REFCLK_OUT pin (see Table 7 for details); default is 01b.
27 Open
26:24 VCO SEL Selects the frequency band of the REFCLK PLL VCO (see Table 8 for details); default is 111b.
23:22
Open
21:19 I
CP
Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 111b.
18:16 Open
15 REFCLK input divider bypass 0 = input divider is selected (default).
1 = input divider is bypassed.
14
REFCLK input divider ResetB
0 = input divider is reset.
1 = input divider operates normally (default).
13:11 Open
10 PFD reset 0 = normal operation (default).
1 = phase detector disabled.
9 Open
8 PLL enable 0 = REFCLK PLL bypassed (default).
1 = REFCLK PLL enabled.
7:1 N This 7-bit number is the divide modulus of the REFCLK PLL feedback divider; default is
0000000b.
0 Open
Auxiliary DAC Control Register—Address 0x03
Four bytes are assigned to this register.
Table 21. Bit Descriptions for DAC Control Register
Bit(s) Mnemonic Description
31:8 Open
7:0 FSC This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary
DAC section); default is 0x7F.