Datasheet

AD9910 Data Sheet
Rev. D | Page 50 of 64
REGISTER MAP AND BIT DESCRIPTIONS
Table 17. Register Map
Register
Name
(Serial
Address)
Bit Range
(Internal
Address)
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
1
(Hex)
CFR1—
Control
Function
Register 1
(0x00)
31:24 RAM
enable
RAM playback
destination
Open 0x00
23:16 Manual
OSK
external
control
Inverse
sinc filter
enable
Open Internal profile control Select DDS
sine output
0x00
15:8 Load LRR
@ I/O
update
Autoclear
digital
ramp
accumu-
lator
Autoclear
phase
accumu-
lator
Clear
digital
ramp
accumu-
lator
Clear
phase
accumu-
lator
Load ARR
@ I/O
update
OSK
enable
Select auto
OSK
0x00
7:0 Digital
power-
down
DAC
power-
down
REFCLK
input
power-
down
Aux DAC
power-
down
External
power-
down
control
Open SDIO input
only
LSB first 0x00
CFR2—
Control
Function
Register 2
(0x01)
31:24 Open Enable
amplitude
scale from
single tone
profiles
0x00
23:16 Internal
I/O
update
active
SYNC_CLK
enable
Digital ramp destination Digital
ramp
enable
Digital
ramp
no-dwell
high
Digital
ramp
no-dwell
low
Read
effective
FTW
0x40
15:8 I/O update rate control Open PDCLK
enable
PDCLK
invert
TxEnable
invert
Open 0x08
7:0 Matched
latency
enable
Data
assembler
hold last
value
Sync
timing
validation
disable
Parallel
data port
enable
FM gain 0x20
CFR3—
Control
Function
Register 3
(0x02)
31:24 Open DRV0[1:0] Open VCO SEL[2:0] 0x1F
23:16 Open I
CP
[2:0] Open 0x3F
15:8 REFCLK
input
divider
bypass
REFCLK
input
divider
ResetB
Open PFD reset Open PLL enable 0x40
7:0
N[6:0]
Open
0x00
Auxiliary
DAC
Control
(0x03)
31:24 Open 0x00
23:16 Open 0x00
15:8 Open 0x00
7:0 FSC[7:0] 0x7F
I/O Update
Rate (0x04)
31:24 I/O update rate[31:24] 0xFF
23:16 I/O update rate[23:16] 0xFF
15:8 I/O update rate[15:8] 0xFF
7:0
I/O update rate[7:0]
0xFF
FTW—
Frequency
Tuning
Word
(0x07)
31:24 Frequency tuning word[31:24] 0x00
23:16 Frequency tuning word[23:16] 0x00
15:8 Frequency tuning word[15:8] 0x00
7:0 Frequency tuning word[7:0] 0x00