Datasheet

Data Sheet AD9910
Rev. D | Page 45 of 64
LVDS
RECEIVER
PROGAMMABLE
DELAY
5
INTERNAL
CLOCKS
CLOCK
STATE
SYNC PULSE
SYSCLK
SETUP AND HOLD
VALIDATION
4
Q0
RESET
Qn
DELAYED SYNC-IN SIGNAL
SYNC
RECEIVER
DELAY
SYNC
RECEIVER
ENABLE
SYNC_SMP_ERR
7
8
12
RISING EDGE
DETECTOR
AND
STROBE
GENERATOR
SYNC
TIMING
VALIDATION
DISABLE
SYNC
VALIDATION
DELAY
06479-052
CLOCK
GENERATOR
•
•
•
•
•
•
SYNC_IN+
SYNC_IN–
Figure 52. Sync Receiver Diagram
SYNC
IN
SYNC
OUT
REF_CLK
AD9910
NUMBER 1
MASTER DEVICE
FPGA
DATA
FPGA
DATA
FPGA
DATA
EDGE
ALIGNED
AT REF_CLK
INPUTS
EDGE
ALIGNED
AT SYNC_IN
INPUTS.
PDCLK
SYNC
IN
SYNC
OUT
REF_CLK
AD9910
NUMBER 2
PDCLK
SYNC
IN
SYNC
OUT
REF_CLK
AD9910
NUMBER 3
PDCLK
(FOR EXAMPLE AD951x)
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
06479-053
CLOCK
SOURCE
Figure 53. Multichip Synchronization Example
The sync receiver accepts a periodic clock signal at the SYNC_
INx pins. This signal is assumed to originate from an LVDS-
compatible driver. The user can delay the SYNC_INx signal in
steps of ~75 ps by programming the 5-bit input sync receiver
delay word in the multichip sync register. The signal at the
output of the programmable delay is referred to as the delayed
SYNC_INx signal.
Note that an internal 100 Ω LVDS termination resistor exists
across both SYNC_IN inputs.
The edge detection logic generates a sync pulse having a dura-
tion of one SYSCLK cycle with a repetition rate equal to the
frequency of the signal applied to the SYNC_INx pins. The
sync pulse is generated as a result of sampling the rising edge
of the delayed SYNC_INx signal with the rising edge of the
local SYSCLK. The sync pulse is routed to the internal clock
generator, which behaves as a presettable counter clocked at the
SYSCLK rate. The sync pulse presets the counter to a predefined
state (programmable via the 6-bit sync state preset value word
in the multichip sync register). The predefined state is only active
for a single SYSCLK cycle, after which the clock generator resumes
cycling through its state sequence at the SYSCLK rate. This
unique state presetting mechanism gives the user the flexibility
to synchronize devices with specific relative clock state offsets
(by assigning a different sync state preset value word to each
device).
Multiple device synchronization is accomplished by providing
each AD9910 with a SYNC_INx signal that is edge aligned