Datasheet

Data Sheet AD9910
Rev. D | Page 3 of 64
Power-Down Control ................................................................. 43
Synchronization of Multiple Devices ............................................ 44
Power Supply Partitioning ............................................................. 47
3.3 V Supplies .............................................................................. 47
DVDD_I/O (3.3 V) (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45,
Pin 56, and Pin 66) .................................................................. 47
AVDD (3.3 V) (Pin 74 to Pin 77 and Pin 83) ...................... 47
1.8 V Supplies .............................................................................. 47
DVDD (1.8 V) (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, and
Pin 64) ...................................................................................... 47
AVDD (1.8 V) (Pin 3)............................................................. 47
AVDD (1.8 V) (Pin 6)............................................................. 47
AVDD (1.8 V) (Pin 89 and Pin 92) ....................................... 47
Serial Programming ........................................................................ 48
Control Interface—Serial I/O .................................................... 48
General Serial I/O Operation .................................................... 48
Instruction Byte ........................................................................... 48
Instruction Byte Information Bit Map ................................. 48
Serial I/O Port Pin Descriptions ............................................... 48
SCLK—Serial Clock................................................................ 48
CS
—Chip Select Bar ............................................................... 48
SDIO—Serial Data Input/Output ......................................... 48
SDO—Serial Data Out ........................................................... 48
I/O_RESET—Input/Output Reset ........................................ 49
I/O_UPDATE—Input/Output Update ................................ 49
Serial I/O Timing Diagrams ...................................................... 49
MSB/LSB Transfers ..................................................................... 49
Register Map and Bit Descriptions ............................................... 50
Register Bit Descriptions............................................................ 55
Control Function Register 1 (CFR1)—Address 0x00 ........ 55
Control Function Register 2 (CFR2)—Address 0x01 ........ 57
Control Function Register 3 (CFR3)—Address 0x02 ........ 58
Auxiliary DAC Control Register—Address 0x03 ............... 58
I/O Update Rate Register—Address 0x04 ........................... 59
Frequency Tuning Word Register (FTW)—Address 0x07 ..... 59
Phase Offset Word Register (POW)—Address 0x08 ......... 59
Amplitude Scale Factor Register (ASF)—Address 0x09 .... 59
Multichip Sync Register—Address 0x0A ............................. 60
Digital Ramp Limit Register—Address 0x0B...................... 60
Digital Ramp Step Size Register—Address 0x0C ............... 60
Digital Ramp Rate Register—Address 0x0D ....................... 60
Profile Registers ...................................................................... 61
Outline Dimensions ........................................................................ 62
Ordering Guide ........................................................................... 62