Datasheet
Data Sheet AD9910
Rev. D | Page 29 of 64
The primary control for the DRG is the digital ramp enable bit.
When disabled, the other DRG input controls are ignored and the
internal clocks are shut down to conserve power.
The output of the DRG is a 32-bit unsigned data bus that can be
routed to any one of the three DDS signal control parameters, as
controlled by the two digital ramp destination bits in Control
Function Register 2 according to Table 11. The 32-bit output
bus is MSB-aligned with the 32-bit frequency parameter, the
16-bit phase parameter, or the 14-bit amplitude parameter, as
defined by the destination bits. When the destination is phase
or amplitude, the unused LSBs are ignored.
Table 11. Digital Ramp Destination
Digital Ramp
Destination Bits
(CFR2[21:20])
DDS Signal
Control
Parameter
Bits Assigned to
DDS Parameter
00 Frequency 31:0
01 Phase 31:16
1x
1
Amplitude 31:18
1
x = Don’t care.
The ramp characteristics of the DRG are fully programmable. This
includes the upper and lower ramp limits, and independent control
of the step size and step rate for both the positive and negative slope
characteristics of the ramp. A detailed block diagram of the DRG is
shown in Figure 38.
The direction of the ramping function is controlled by the
DRCTL pin. A Logic 0 on this pin causes the DRG to ramp
with a negative slope, whereas a Logic 1 causes the DRG to
ramp with a positive slope.
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is set to Logic 1, the DRG is stalled at its last
state; otherwise, the DRG operates normally.
The DDS signal control parameters that are not the destination of
the DRG are taken from the active profile.
DDS CLOCK
D Q
R
LOWER
LIMIT
0
1
DECREMENT STEP SIZE
PRESET
Q
DRCTL
LOAD
CLEAR DIGITAL RAMP ACCUMULATOR
AUTOCLEAR DIGITAL RAMP ACC
.
NO DWELL
LIMIT CONTROL
DIGITAL RAMP ACCUMULATOR
INCREMENT STEP SIZE
32
32
0
1
NEGATIVE SLOPE RATE
POSITIVE SLOPE RATE
16
16
32
16
62
DRHOLD
63
32
32
LOAD
CONTROL
LOGIC
LOAD LRR AT I/O_UPDATE
DIGITAL
RAMP
TIMER
ACCUMULATOR
RESET
CONTROL
LOGIC
NO-DWELL
CONTROL
2
3232
TO DDS
SIGNAL
CONTROL
PARAMETER
UPPER
LIMIT
32
06479-019
Figure 38. Digital Ramp Generator Detail