Datasheet

AD9910 Data Sheet
Rev. D | Page 26 of 64
as well as a programmable charge pump current and external
loop filter components (connected via the PLL_LOOP_FILTER
pin). These features add an extra layer of flexibility to the PLL,
allowing optimization of phase noise performance and
flexibility in frequency plan development. The PLL is also
equipped with a PLL_LOCK pin.
The PLL output frequency range (f
SYSCLK
) is constrained to the
range of 420 MHz ≤ f
SYSCLK
≤ 1 GHz by the internal VCO. In
addition, the user must program the VCO to one of six operating
ranges such that f
SYSCLK
falls within the specified range. Figure 33
and Figure 34 summarize these VCO ranges.
Figure 33 shows the boundaries of the VCO frequency ranges
over the full range of temperature and supply voltage variation
for all devices from the available population. The implication is
that multiple devices chosen at random from the population and
operated under widely varying conditions may require different
values to be programmed into CFR3[26:24] to operate at the
same frequency. For example, Part A chosen randomly from the
population, operating at an ambient temperature of −10°C with
a system clock frequency of 900 MHz may require CFR3[26:24] to
be set to 100b, whereas Part B chosen randomly from the
population, operating at an ambient temperature of 90°C with a
system clock frequency of 900 MHz may require CFR3[26:24]
to be set to 101b. If a frequency plan is chosen such that the
system clock frequency operates within one set of boundaries
(as shown in Figure 33), the required value in CFR3[26:24] is
consistent from part to part.
Figure 34 shows the boundaries of the VCO frequency ranges
over the full range of temperature and supply voltage variation
for an individual device selected from the population. Figure 34
shows that the VCO frequency ranges for a single device always
overlap when operated over the full range of conditions.
If a user wants to retain a single default value for CFR3[26:24],
a frequency that falls into one of the ranges found in Figure 33
should be selected. Additionally, for any given individual device,
the VCO frequency ranges overlap, meaning that any given
device exhibits no gaps in its frequency coverage across VCO
ranges over the full range of conditions.
06479-059
VCO0
VCO1
VCO2
VCO3
VCO4
VCO5
395 495 595 695 795 895 995
f
LOW
= 400
f
HIGH
= 460
f
LOW
= 455
f
HIGH
= 530
f
LOW
= 530
f
HIGH
= 615
f
LOW
= 760
f
HIGH
= 875
f
LOW
= 920
f
HIGH
= 1030
f
LOW
= 650
f
HIGH
= 790
(MHz)
Figure 33. VCO Ranges Including Atypical Wafer Process Skew
335 435 535 635 735 835 935 1035 1135
VCO0
VCO1
VCO2
VCO3
VCO4
VCO5
06479-060
f
LOW
= 370
f
HIGH
= 510
f
LOW
= 420
f
HIGH
= 590
f
LOW
= 500
f
HIGH
= 700
f
LOW
= 700
f
HIGH
= 950
f
LOW
= 820
f
HIGH
= 1150
f
LOW
= 600
f
HIGH
= 880
(MHz)
Figure 34. Typical VCO Ranges
Table 8. VCO Range Bit Settings
VCO SEL Bits (CFR3[26:24]) VCO Range
000 VCO0
001 VCO1
010 VCO2
011 VCO3
100 VCO4
101 VCO5
110 PLL bypassed
111 PLL bypassed
PLL Charge Pump
The charge pump current (I
CP
) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 9 lists the bit settings vs. the nominal charge pump current.
Table 9. PLL Charge Pump Current
I
CP
Bits (CFR3[21:19]) Charge Pump Current, I
CP
(μA)
000 212
001 237
010 262
011 287
100 312
101 337
110 363
111 387