Datasheet

Data Sheet AD9910
Rev. D | Page 25 of 64
REF_CLK
REF_CLK
PLL
VCO
SELECT
DIVIDE
CHARGE
PUMP
OUTIN
PLL_LOOP_FILTERENABLE
PLL_LOOP_FILTER
DRV0
CFR3
[29:28]
REFCLK_OUT
XTAL_SEL
REFCLK
INPUT
SELECT
LOGIC
SYSCLK
I
CP
CFR3
[21:19]
N
CFR3
[7:1]
VCO SEL
CFR3
[26:24]
÷2
REFCLK
INPUT DIVIDER BYPASS
CFR3[15]
PLL ENABLE
CFR3
[8]
REFCLK
INPUT DIVIDER
RESETB
CFR3[14]
94
95
2
90
91
0
1
0
1
2
2
7
3
0
1
06479-013
Figure 30. REF_CLK Block Diagram
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected,
the REF_CLK/
REF_CLK
pins must be driven by an external
signal source (single-ended or differential). Input frequencies
up to 2 GHz are supported. For input frequencies greater than
1 GHz, the input divider must be enabled for proper operation
of the device.
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT has
programmable drive capability. This is controlled by two bits, as
listed in Table 7.
Table 7. REFCLK_OUT Buffer Control
DRV0 Bits (CFR3[29:28]) REFCLK_OUT Buffer
00 Disabled (tristate)
01 Low output current
10 Medium output current
11 High output current
Crystal Driven REF_CLK/
REF_CLK
When using a crystal at the REF_CLK/
REF_CLK
input, the
resonant frequency should be approximately 25 MHz. Figure 31
shows the recommended circuit configuration. The internal
oscillator works with fundamental mode crystals only. Crystal
operation is enabled by a Logic 1 (1.8 V logic required) on the
XTAL_SEL pin.
06479-014
REF_CLK
REF_CLK
39pF39pF
XTAL
90
91
Figure 31. Crystal Connection Diagram
Direct Driven REF_CLK/
REF_CLK
When driving the REF_CLK/
REF_CLK
inputs directly from a
signal source, either single-ended or differential signals can be
used. With a differential signal source, the REF_CLK/
REF_CLK
pins are driven with complementary signals and ac-coupled with
0.1 µF capacitors. With a single-ended signal source, either a
single-ended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 µF capacitors are used to ac couple both REF_CLK/
REF_CLK
pins to avoid disturbing the internal dc bias voltage
of ~1.35 V. See Figure 32 for more details.
The REF_CLK/
REF_CLK
input resistance is ~2.5 kΩ differential
(~1.2 kΩ single-ended). Most signal sources have relatively low
output impedances. The REF_CLK/
REF_CLK
input resistance
is relatively high; therefore, its effect on the termination impedance
is negligible and can usually be chosen to be the same as the
output impedance of the signal source. The bottom two examples
in
Figure 32 assume a signal source with a 50 Ω output
impedance.
06479-015
TERMINATION
REF_CLK
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT
90
91
0.1µF
0.1µF
PECL,
LVPECL,
OR
LVDS
DRIVER
REF_CLK
90
91
50Ω
0.1µF
0.1µF
BALUN
(1:1)
REF_CLK
REF_CLK
REF_CLK
REF_CLK
90
91
0.1µF
0.1µF
50Ω
Figure 32. Direct Connection Diagram
Phase-Locked Loop (PLL) Multiplier
An internal phase-locked loop (PLL) provides the option to use
a reference clock frequency that is significantly lower than the
system clock frequency. The PLL supports a wide range of
programmable frequency multiplication factors (12× to 127×)