Datasheet

Data Sheet AD9910
Rev. D | Page 23 of 64
FUNCTIONAL BLOCK DETAIL
DDS CORE
The direct digital synthesizer (DDS) block generates a reference
signal (sine or cosine based on CFR1[16], the select DDS sine
output bit). The parameters of the reference signal (frequency,
phase, and amplitude) are applied to the DDS at its frequency,
phase offset, and amplitude control inputs, as shown in Figure 27.
06479-010
DDS_CLK
32 19
FREQUENCY
CONTROL
ANGLE-TO-
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
PHASE
OFFSET
CONTROL
TO DAC
(MSBs)
D Q
R
ACCUMULATOR
RESET
32
16
MSB ALIGNED
AMPLITUDE
CONTROL
14
DDS SIGNAL CONTROL PARAMETERS
16
1419
32
32
14
14
32-BIT
ACCUMULATOR
Figure 27. DDS Block Diagram
The output frequency (f
OUT
) of the AD9910 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. The relationship among f
OUT
, FTW, and f
SYSCLK
is given by
SYSCLK
OUT
f
FTW
f






=
32
2
(1)
where FTW is a 32-bit integer ranging in value from 0 to
2,147,483,647 (2
31
− 1), which represents the lower half of the
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, ½ f
SYSCLK
).
The FTW required to generate a desired value of f
OUT
is found
by solving Equation 1 for FTW, as given in Equation 2.
















=
SYSCLK
OUT
f
f
FTW
32
2round
(2)
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value. For example, for f
OUT
=
41 MHz and f
SYSCLK
= 122.88 MHz, then FTW = 1,433,053,867
(0x556AAAAB).
Programming an FTW greater than 2
31
produces an aliased
image that appears at a frequency given by
SYSCLK
OUT
f
FTW
f






−=
32
2
1
(for FTW ≥ 2
31
)
The relative phase of the DDS signal can be digitally controlled
by means of a 16-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by












=
16
16
2
360
2
2
Δ
POW
POW
π
θ
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the POW
value necessary to develop an arbitrary Δθ, solve the previous
equation for POW and round the result (in a manner similar
to that described previously for finding an arbitrary FTW).
The relative amplitude of the DDS signal can be digitally scaled
(relative to full scale) by means of a 14-bit amplitude scale
factor (ASF). The amplitude scale value is applied at the output
of the angle-to-amplitude conversion block internal to the DDS
core. The amplitude scale is given by






=
14
14
2
log20
2
ASF
ASF
ScaleAmplitude
(3)
where the upper quantity is amplitude expressed as a fraction of
full scale and the lower quantity is expressed in decibels relative
to full scale. To find the ASF value necessary for a particular
scale factor, solve Equation 3 for ASF and round the result (in
a manner similar to that described previously for finding an
arbitrary FTW).
When the AD9910 is programmed to modulate any of the DDS
signal control parameters, the maximum modulation sample
rate is ¼ f
SYSCLK
. This means that the modulation signal exhibits
images at multiples of ¼ f
SYSCLK
. The impact of these images
must be considered when using the device as a modulator.
14-BIT DAC OUTPUT
The AD9910 incorporates an integrated 14-bit, current output
DAC. The output current is delivered as a balanced signal using
two outputs. The use of balanced outputs reduces the potential
amount of common-mode noise present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. An
external resistor (R
SET
) connected between the DAC_RSET pin
and AGND establishes the reference current. The full-scale
output current of the DAC (I
OUT
) is produced as a scaled version
of the reference current (see the Auxiliary DAC section). The
recommended value of R
SET
is 10 kΩ.
Attention should be paid to the load termination to keep the
output voltage within the specified compliance range; voltages
developed beyond this range cause excessive distortion and can
damage the DAC output circuitry.