Datasheet

Data Sheet AD9910
Rev. D | Page 21 of 64
Table 4. Parallel Port Destination Bits
F[1:0] D[15:0] Parameter(s) Comments
00 D[15:2] 14-bit amplitude
parameter (unsigned
integer)
Amplitude scales from 0 to 1 − 2
−14
. D[1:0] are not used.
01 D[15:0] 16-bit phase parameter
(unsigned integer)
Phase offset ranges from 0 to 2π(1 − 2
−16
) radians.
10 D[15:0] 32-bit frequency
parameter (unsigned
integer)
The alignment of the 16-bit data-word with the 32-bit frequency parameter is controlled
by a 4-bit FM gain word in the programming registers.
11 D[15:8] 8-bit amplitude
(unsigned integer)
The MSB of the data-word amplitude aligns with the MSB of the DDS 14-bit amplitude
parameter. The six LSBs of the DDS amplitude parameter are assigned from Bits[5:0] of the
ASF register. The resulting 14-bit word scales the amplitude from 0 to 1 − 2
−14
.
D[7:0] 8-bit phase (unsigned
integer)
The MSB of the data-word phase aligns with the MSB of the 16-bit phase parameter of
the DDS. The eight LSBs of the DDS phase parameter are assigned from Bits[7:0] of the
POW register. The resulting 16-bit word offsets the phase from 0 to 2π(1 − 2
−16
) radians.
Transmit Enable (TxENABLE)
The AD9910 also accepts a user-generated signal applied to the
TxENABLE pin that acts as a gate for the user-supplied data. By
default, TxENABLE is considered true for Logic 1 and false for
Logic 0. However, the logical behavior of this pin can be reversed
using the TxENABLE invert bit. When TxENABLE is true, the
device latches data into the device on the expected edge of PDCLK
(based on the PDCLK invert bit). When TxENABLE is false,
even though the PDCLK may continue to operate, the device
ignores the data supplied to the port. Furthermore, when the
TxENABLE pin is held false, the device internally clears the
16-bit data-words, or it retains the last value present on the data
port prior to TxENABLE switching to the false state (based on
the setting of the data assembler hold last value bit).
Alternatively, instead of operating the TxENABLE pin as a gate,
the user can drive the TxENABLE pin with a clock signal
operating at the parallel port data rate. When driven by a clock
signal, the transition from the false to true state must meet the
required setup and hold time on each cycle to ensure proper
operation. The TxENABLE and PDCLK timing is shown in
Figure 26.
06479-009
FALSE
TRUE
TxENABLE
(BURST)
TxENABLE
(CLOCK)
WORD
1
WORD
2
WORD
3
WORD
4
WORD
N – 4
WORD
N
PDCLK
PARALLEL
DATA PORT
t
DS
t
DS
t
DH
t
DH
Figure 26. PDCLK and TxENABLE Timing Diagram