Datasheet
AD9910 Data Sheet
Rev. D | Page 18 of 64
RAM MODULATION MODE
The RAM modulation mode (see Figure 23) is activated via the
RAM enable bit and assertion of the I/O_UPDATE pin (or a
profile change). In this mode, the modulated DDS signal control
parameters are supplied directly from RAM.
The RAM consists of 32-bit words and is 1024 words deep.
Coupled with a sophisticated internal state machine, the RAM
provides a very flexible method for generating arbitrary, time
dependent waveforms. A programmable timer controls the rate
at which words are extracted from the RAM for delivery to the
DDS. Thus, the programmable timer establishes a sample rate at
which 32-bit samples are supplied to the DDS.
The selection of the specific DDS signal control parameters that
serve as the destination for the RAM samples is also programmable
through eight independent RAM profile registers. Select a par-
ticular profile using the three external profile pins (PROFILE[2:0]).
A change in the state of the profile pins with the next rising
edge on SYNC_CLK activates the selected RAM profile.
In RAM modulation mode, the ability to generate a time depen-
dent amplitude, phase, or frequency signal enables modulation
of any one of the parameters controlling the DDS carrier signal.
Furthermore, a polar modulation format is available that partitions
each RAM sample into a magnitude and phase component; 16 bits
are allocated to phase and 14 bits are allocated to magnitude.
06479-006
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK
A
θ
INVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SERIAL I/O PORT
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYNC_SMP_ERR
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
DDS
AUX
DAC
8-BIT
DAC
14-BIT
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
SYNC_CLK
POWER-
DOWN
CONTROL
Figure 23. RAM Modulation Mode