Datasheet

AD9910 Data Sheet
Rev. D | Page 16 of 64
APPLICATION CIRCUITS
LOOP
FILTER
PHASE
COMPARATOR
VCO
AD9910
REF_CLK
REFERENCE
CHARGE
PUMP
AD9510, AD9511, ADF4106
÷
÷
06479-056
LPF
Figure 19. DDS in PLL Feedback Locking to Reference, Offering Fine Frequency and Delay Adjust Tuning
AD9910
(SLAVE 1)
AD9910
(MASTER)
CLOCK
SOURCE
AD9910
(SLAVE 2)
AD9910
(SLAVE 3)
FPGA
DATA
SYNC_CLK
REF_CLK
SYNC_CLK
SYNC_CLK
FPGA
DATA
FPGA
DATA
DATA
FPGA
SYNC_CLK
C1
S1
C2
S2
C3
S3
C4
S4
A1
A2
A4
A3
A_END
CENTRAL
CONTROL
AD9510
CLOCK DISTRIBUTOR
WITH
DELAY EQUALIZATION
SYNC_OUT
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
06479-058
Figure 20. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and Synchronization Clock
AD9910
REFCLK
n
PROGRAMMABLE 1 TO 32
DIVIDER AND DELAY ADJUST
CLOCK OUTPUT
SELECTION(S)
n = DEPENDENT ON PRODUCT SELECTION.
AD9515
AD9514
AD9513
AD9512
LVPECL
LVDS
CMOS
CH 2
06479-057
LPF
Figure 21. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips