GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer AD9910 Data Sheet FEATURES APPLICATIONS 1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS, 14-bit DAC 0.
AD9910 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 External PLL Loop Filter Components ............................... 27 Applications ....................................................................................... 1 PLL Lock Indication .................................................................. 27 Functional Block Diagram ..............................................................
Data Sheet AD9910 Power-Down Control .................................................................43 SDO—Serial Data Out ........................................................... 48 Synchronization of Multiple Devices............................................44 I/O_RESET—Input/Output Reset ........................................ 49 Power Supply Partitioning .............................................................47 I/O_UPDATE—Input/Output Update ................................ 49 3.
AD9910 Data Sheet REVISION HISTORY 5/12—Rev. C to Rev. D Changes to Table 1 ............................................................................ 8 Changes to Table 3 .......................................................................... 12 Changes to Figure 39 ...................................................................... 31 Changes to Synchronization of Multiple Devices Section ........ 45 Changes to Table 18 ........................................................................
Data Sheet AD9910 GENERAL DESCRIPTION The AD9910 is controlled by programming its internal control registers via a serial I/O port. The AD9910 includes an integrated static RAM to support various combinations of frequency, phase, and/or amplitude modulation. The AD9910 also supports a user defined, digitally controlled, digital ramp mode of operation. In this mode, the frequency, phase, or amplitude can be varied linearly over time.
AD9910 Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) = 3.3 V ± 5%, DVDD_I/O (3.3 V) = 3.3 V ± 5%, T = 25°C, RSET = 10 kΩ, IOUT = 20 mA, external reference clock frequency = 1000 MHz with reference clock (REFCLK) multiplier disabled, unless otherwise noted. Table 1.
Data Sheet Parameter 201.1 MHz Analog Output 301.1 MHz Analog Output 401.
AD9910 Parameter CMOS LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance XTAL_SEL INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance CMOS LOGIC OUTPUTS Logic 1 Voltage Logic 0 Voltage POWER SUPPLY CURRENT IAVDD (1.8 V) IAVDD (3.3 V) IDVDD (1.8 V) IDVDD (3.3 V) TOTAL POWER CONSUMPTION Single Tone Mode Rapid Power-Down Mode Full Sleep Mode Data Sheet Conditions/Comments Min Typ Max Unit 0.8 150 150 V V µA µA pF 0.6 V V pF 2.0 90 90 2 1.
Data Sheet AD9910 ABSOLUTE MAXIMUM RATINGS EQUIVALENT CIRCUITS DAC OUTPUTS Rating 2V 4V −0.7 V to +4 V −0.7 V TO +2.2 V 5 mA −65°C to +150°C −40°C to +85°C 22°C/W 2.8°C/W 150°C 300°C AVDD IOUT IOUT MUST TERMINATE OUTPUTS TO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. 06479-003 Parameter AVDD (1.8V), DVDD (1.8V) Supplies AVDD (3.3V), DVDD_I/O (3.
AD9910 Data Sheet 76 AVDD (3.3V) 78 AGND 77 AVDD (3.3V) 79 AGND 81 IOUT 80 IOUT 82 AGND 83 AVDD (3.3V) 84 DAC_RSET 86 NC 85 AGND 87 NC 88 AGND 89 AVDD (1.8V) 91 REF_CLK 90 REF_CLK 92 AVDD (1.8V) 93 NC 94 REFCLK_OUT 96 AGND 95 XTAL_SEL 97 NC 99 NC 98 NC 100 NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 75 AVDD (3.3V) NC 1 PLL_LOOP_FILTER 2 AVDD (1.8V) 3 AGND 4 AGND 5 AVDD (1.
Data Sheet AD9910 Table 3. Pin Function Descriptions Pin No. 1, 20, 72, 86, 87, 93, 97 to 100 2 Mnemonic NC I/O 1 Description Not Connected. Allow device pins to float. PLL_LOOP_FILTER I 3, 6, 89, 92 74 to 77, 83 17, 23, 30, 47, 57, 64 11, 15, 21, 28, 45, 56, 66 4, 5, 73, 78, 79, 82, 85, 88, 96 13, 16, 22, 29, 46, 51, 58, 65 7 AVDD (1.8V) AVDD (3.3V) DVDD (1.8V) I I I PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for details. Analog Core VDD, 1.
AD9910 Data Sheet Pin No. 59 Mnemonic I/O_UPDATE I/O 1 I/O 60 OSK I 61 DROVER O 62 DRCTL I 63 DRHOLD I 67 SDIO I/O 68 SDO O 69 SCLK I 70 CS I 71 I/O_RESET I 80 IOUT O 81 IOUT O 84 DAC_RSET O 90 REF_CLK I 91 94 95 REF_CLK REFCLK_OUT XTAL_SEL I O I EPAD Exposed Paddle (EPAD) 1 Description Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the I/O buffers to the corresponding internal registers. Output Shift Keying.
Data Sheet AD9910 TYPICAL PERFORMANCE CHARACTERISTICS –50 0 –10 –55 –20 –30 –60 SFDR (dBc) SFDR (dBc) SFDR WITHOUT PLL SFDR WITH PLL –65 –40 –50 –60 1 –70 –70 0 50 100 150 200 250 300 350 400 06479-035 06479-034 –75 –80 –90 –100 50MHz/DIV START 0Hz STOP 500MHz OUTPUT FREQUENCY (MHz) Figure 6. Wideband SFDR vs. Output Frequency (PLL with Reference Clock = 15.625 MHz × 64) Figure 9.
Data Sheet 0 0 –12 –12 –24 –24 –36 –36 –48 –48 SFDR (dBc) –60 –72 –72 –84 –84 1 –120 2.5kHz/DIV 06479-040 –108 CENTER 10.32MHz 1 –96 06479-038 –96 –108 –120 CENTER 403.78MHz SPAN 25kHz 0 –90 –12 –100 –24 MAGNITUDE (dBc/Hz) –48 –60 –72 –84 –120 fOUT = 98.6MHz –130 –140 –160 fOUT = 20.1MHz 06479-039 –108 –120 2.5kHz/DIV fOUT = 201.1MHz –150 1 CENTER 204.36MHz SPAN 25kHz fOUT = 397.8MHz –110 –36 –96 2.5kHz/DIV Figure 14. Narrow-Band SFDR at 403.
Data Sheet AD9910 –90 450 fOUT = 397.8MHz –120 –130 –140 fOUT = 98.6MHz 100 1k 10k 100k 1M 10M 06479-043 fOUT = 20.1MHz –150 DVDD 1.8V 300 250 200 AVDD 1.8V 150 100 AVDD 3.3V 50 DVDD 3.3V 400 500 600 700 800 900 06479-044 POWER DISSIPATION (mW) 350 300 AVDD 1.8V 200 150 100 AVDD 3.3V 50 DVDD 3.3V 500 600 700 800 900 1000 Figure 18. Power Dissipation vs. System Clock Frequency (PLL Enabled) 450 200 250 SYSTEM CLOCK FREQUENCY (MHz) Figure 16.
AD9910 Data Sheet APPLICATION CIRCUITS AD9510, AD9511, ADF4106 ÷ REFERENCE CHARGE PUMP PHASE COMPARATOR LOOP FILTER VCO AD9910 06479-056 ÷ REF_CLK LPF Figure 19.
Data Sheet AD9910 THEORY OF OPERATION A separate output shift keying (OSK) function is also available. This function employs a separate digital linear ramp generator that only affects the amplitude parameter of the DDS. The OSK function has priority over the other data sources that can drive the DDS amplitude parameter. As such, no other data source can drive the DDS amplitude when the OSK function is enabled. The AD9910 has four modes of operation.
AD9910 Data Sheet The selection of the specific DDS signal control parameters that serve as the destination for the RAM samples is also programmable through eight independent RAM profile registers. Select a particular profile using the three external profile pins (PROFILE[2:0]). A change in the state of the profile pins with the next rising edge on SYNC_CLK activates the selected RAM profile.
Data Sheet AD9910 The ramp is digitally generated with 32-bit output resolution. The 32-bit output of the DRG can be programmed to represent frequency, phase, or amplitude. When programmed to represent frequency, all 32 bits are used. However, when programmed to represent phase or amplitude, only the 16 MSBs or 14 MSBs, respectively, are used.
AD9910 Data Sheet apply a weighting factor to the 16-bit data-word. In the default state (0), the 16-bit data-word and the 32-bit word in the FTW register are LSB aligned. Each increment in the value of the FM gain word shifts the 16-bit data-word to the left relative to the 32-bit word in the FTW register, increasing the influence of the 16-bit data-word on the frequency defined by the FTW register by a factor of two. The FM gain word effectively controls the frequency range spanned by the data-word.
Data Sheet AD9910 Table 4. Parallel Port Destination Bits D[15:0] D[15:2] 01 D[15:0] 10 D[15:0] 11 D[15:8] D[7:0] Parameter(s) 14-bit amplitude parameter (unsigned integer) 16-bit phase parameter (unsigned integer) 32-bit frequency parameter (unsigned integer) 8-bit amplitude (unsigned integer) 8-bit phase (unsigned integer) Comments Amplitude scales from 0 to 1 − 2−14. D[1:0] are not used. Phase offset ranges from 0 to 2π(1 − 2−16) radians.
AD9910 Data Sheet MODE PRIORITY The three different modulation modes generate frequency, phase, and/or amplitude data destined for the DDS signal control parameters. In addition, the OSK function generates amplitude data destined for the DDS. Each of these functions is independently invoked using the appropriate control bit via the serial I/O port.
Data Sheet AD9910 FUNCTIONAL BLOCK DETAIL POW 2π 16 2 Δθ = POW 360 16 2 DDS CORE The direct digital synthesizer (DDS) block generates a reference signal (sine or cosine based on CFR1[16], the select DDS sine output bit). The parameters of the reference signal (frequency, phase, and amplitude) are applied to the DDS at its frequency, phase offset, and amplitude control inputs, as shown in Figure 27.
AD9910 Data Sheet Auxiliary DAC 1 An 8-bit auxiliary DAC controls the full-scale output current of the main DAC (IOUT). An 8-bit code word stored in the appropriate register map location sets IOUT according to the following equation: 0 86.4 CODE 1 + 96 RSET –1 (dB) IOUT = SINC –2 where RSET is the value of the RSET resistor (in ohms) and CODE is the 8-bit value supplied to the auxiliary DAC (default is 127). For example, with RSET = 10,000 Ω and CODE = 127, then IOUT = 20.07 mA.
Data Sheet AD9910 XTAL_SEL PLL_LOOP_FILTER 95 2 DRV0 CFR3 [29:28] 2 90 REF_CLK XTAL PLL ENABLE CFR3 [8] REFCLK INPUT SELECT LOGIC 91 REF_CLK 39pF ENABLE PLL_LOOP_FILTER IN REF_CLK 90 CHARGE PUMP DIVIDE REF_CLK 91 2 1 ÷2 0 REFCLK INPUT DIVIDER RESETB CFR3[14] ICP CFR3 [21:19] OUT PLL VCO SELECT 7 N CFR3 [7:1] 1 0 SYSCLK 3 VCO SEL CFR3 [26:24] REFCLK INPUT DIVIDER BYPASS CFR3[15] 06479-013 1 0 Figure 30.
AD9910 Data Sheet as well as a programmable charge pump current and external loop filter components (connected via the PLL_LOOP_FILTER pin). These features add an extra layer of flexibility to the PLL, allowing optimization of phase noise performance and flexibility in frequency plan development. The PLL is also equipped with a PLL_LOCK pin.
Data Sheet AD9910 External PLL Loop Filter Components PLL LOCK INDICATION The PLL_LOOP_FILTER pin provides a connection interface to attach the external loop filter components. The ability to use custom loop filter components gives the user more flexibility to optimize the PLL performance. The PLL and external loop filter components are shown in Figure 35. When the PLL is in use, the PLL_LOCK pin provides an active high indication that the PLL has locked to the REFCLK input signal.
AD9910 Data Sheet Automatic OSK Table 10. OSK Amplitude Step Size In automatic mode, the OSK function automatically generates a linear amplitude vs. time profile (or amplitude ramp). The amplitude ramp is controlled via three parameters: the maximum amplitude scale factor, the amplitude step size, and the time interval between steps. The amplitude ramp parameters reside in the 32-bit ASF register and are programmed via the serial I/O port.
Data Sheet AD9910 The primary control for the DRG is the digital ramp enable bit. When disabled, the other DRG input controls are ignored and the internal clocks are shut down to conserve power. The ramp characteristics of the DRG are fully programmable. This includes the upper and lower ramp limits, and independent control of the step size and step rate for both the positive and negative slope characteristics of the ramp. A detailed block diagram of the DRG is shown in Figure 38.
AD9910 Data Sheet DRG Slope Control The core of the DRG is a 32-bit accumulator clocked by a programmable timer. The time base for the timer is the DDS clock, which operates at ¼ fSYSCLK. The timer establishes the interval between successive updates of the accumulator.
Data Sheet AD9910 P DDS CLOCK CYCLES N DDS CLOCK CYCLES 1 DDS CLOCK CYCLE NEGATIVE STEP SIZE +Δt POSITIVE STEP SIZE –Δt UPPER LIMIT DRG OUTPUT LOWER LIMIT DROVER DRHOLD AUTO CLEAR CLEAR DRCTL RELEASE DIGITAL RAMP ENABLE CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR I/O_UPDATE 2 3 4 5 6 7 8 9 11 10 13 12 06479-020 1 Figure 39.
AD9910 Data Sheet No-Dwell Ramp Generation P DDS CLOCK CYCLES During no-dwell operation, the DRCTL pin is monitored for state transitions only; that is, the static logic level is immaterial. During no-dwell high operation, a positive transition of the DRCTL pin initiates a positive slope ramp, which continues uninterrupted (regardless of any further activity on the DRCTL pin) until the upper limit is reached.
Data Sheet AD9910 3. Write to (or read from) the RAM (Address 0x16) the appropriate number of RAM words as specified by the selected RAM profile control register (see the Serial Programming section for details). Figure 41 is a block diagram showing the functional components used for RAM data load/retrieve operation.
AD9910 Data Sheet WAVEFORM START ADDRESS WAVEFORM END ADDRESS ADDRESS RAMP RATE RAM MODE NO DWELL 3 10 UP/DOWN COUNTER U/D Q 10 RAM_SWP_OVR (RAM Sweep Over) Pin RAM 32 The RAM_SWP_OVR pin provides an active high external signal that indicates the end of a playback sequence. The operation of this pin varies with the RAM operating mode as detailed in the following sections. When RAM enable = 0, this pin is forced to a Logic 0.
Data Sheet AD9910 RAM Direct Switch Mode with Zero Crossing The zero-crossing function (enabled with the zero-crossing bit) is a special feature that is only available in RAM direct switch mode. The zero-crossing function is only valid if the RAM playback destination bits specify phase as the DDS signal control parameter. Ramp-Up Timing Diagram A graphic representation of the ramp-up mode appears in Figure 43, showing both normal and no-dwell operation.
AD9910 Data Sheet RAM Ramp-Up Internal Profile Control Mode Table 14. RAM Internal Profile Control Modes Internal Profile Control Bits (CFR1[20:17]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Waveform Type Internal Profile Control Description Internal profile control disabled. Execute Profile 0, then Profile 1, then halt. Execute Profile 0 to Profile 2, then halt. Execute Profile 0 to Profile 3, then halt. Execute Profile 0 to Profile 4, then halt.
Data Sheet AD9910 RAM PROFILE 0 1 2 WAVEFORM END ADDRESS 2 Δt2 WAVEFORM START ADDRESS 2 1 Δt1 WAVEFORM END ADDRESS 1 RAM ADDRESS WAVEFORM START ADDRESS 1 1 WAVEFORM END ADDRESS 0 Δt0 1 WAVEFORM START ADDRESS 0 RAM_SWP_OVER 1 2 3 4 5 6 7 06479-025 I/O_UPDATE Figure 44. Internal Profile Control Timing Diagram (Burst) The gray bar across the top indicates the time interval over which the designated profile is in effect.
AD9910 Data Sheet 0 RAM PROFILE 1 0 1 1 Δt1 WAVEFORM END ADDRESS 1 1 WAVEFORM START ADDRESS 1 RAM ADDRESS 0 WAVEFORM END ADDRESS 0 Δt0 1 WAVEFORM START ADDRESS 0 RAM_SWP_OVER 1 2 3 4 5 6 7 8 9 10 11 06479-026 I/O_UPDATE Figure 45. Internal Profile Control Timing Diagram (Continuous) Internal Profile Control Continuous Waveform Timing Diagram Profile 0 and begins incrementing through the address range for RAM Profile 0 at intervals of Δt0.
Data Sheet AD9910 M DDS CLOCK CYCLES Δt WAVEFORM END ADDRESS RAM ADRESS Δt 1 WAVEFORM START ADDRESS RAM_SWP_OVER PROFILE0 1 2 3 4 5 6 7 8 06479-027 I/O_UPDATE Figure 46. Bidirectional Ramp Timing Diagram If the PROFILE0 pin changes states before the state machine reaches the programmed start or end address, the internal timer is restarted and the direction of the address counter is reversed. Event 6—Pin PROFILE0 switches to Logic 0.
AD9910 Data Sheet M DDS CLOCK CYCLES RAM ADRESS Δt Δt WAVEFORM END ADDRESS 1 WAVEFORM START ADDRESS I/O_UPDATE 2 1 3 06479-028 RAM_SWP_OVER Figure 47. Continuous Bidirectional Ramp Timing Diagram A change in state of the PROFILE pins aborts the current waveform, and the newly selected RAM profile is used to initiate a new waveform.
Data Sheet AD9910 M DDS CLOCK CYCLES Δt WAVEFORM END ADDRESS RAM ADRESS 1 WAVEFORM START ADDRESS RAM_SWP_OVER 1 2 3 4 5 06479-029 I/O_UPDATE Figure 48. Continuous Recirculate Timing Diagram RAM Continuous Recirculate Mode The continuous recirculate mode mimics the ramp-up mode, except that when the state machine reaches the waveform end address, the next timeout of the internal timer causes the state machine to jump to the waveform start address.
AD9910 Data Sheet ADDITIONAL FEATURES PROFILES The AD9910 supports the use of profiles, which consist of a group of eight registers containing pertinent operating parameters for a particular operating mode. Profiles enable rapid switching between parameter sets. Profile parameters are programmed via the serial I/O port. Once programmed, a specific profile is activated by means of three external pins (PROFILE[2:0]).
Data Sheet AD9910 AUTOMATIC I/O UPDATE POWER-DOWN CONTROL The AD9910 offers an option whereby the I/O update function is asserted automatically rather than relying on an external signal supplied by the user. This feature is enabled by setting the internal I/O update active bit in Control Function Register 2 (CFR2). The AD9910 offers the ability to independently power down four specific sections of the device.
AD9910 Data Sheet SYNCHRONIZATION OF MULTIPLE DEVICES The function of the synchronization logic in the AD9910 is to force the internal clock generator to a predefined state coincident with an external synchronization signal applied to the SYNC_INx pins. If all devices are forced to the same clock state in synchronization with the same external signal, then the devices are, by definition, synchronized. Figure 50 is a block diagram of the synchronization function.
Data Sheet AD9910 CLOCK STATE SYNC RECEIVER ENABLE DELAYED SYNC-IN SIGNAL LVDS RECEIVER 7 SYNC_IN– 8 Q0 • • • RISING EDGE DETECTOR AND STROBE GENERATOR PROGAMMABLE DELAY SYNC TIMING VALIDATION DISABLE INTERNAL CLOCKS Qn RESET CLOCK GENERATOR SETUP AND HOLD VALIDATION SYNC_SMP_ERR 12 • • • SYSCLK 4 SYNC VALIDATION DELAY SYNC PULSE 06479-052 SYNC_IN+ SYNC RECEIVER DELAY 5 Figure 52.
AD9910 Data Sheet assume the same predefined clock state simultaneously; that is, the internal clocks of all devices become fully synchronized. across all the devices. If the SYNC_INx signal is edge aligned at all devices, and all devices have the same sync receiver delay and sync state preset value, then they all have matching clock states (that is, they are synchronized).
Data Sheet AD9910 POWER SUPPLY PARTITIONING The AD9910 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The values quoted in this section are for comparison only. Refer to Table 1 for exact values. With each group, use 0.1 μF or 0.01 μF bypass capacitors in parallel with a 10 μF capacitor.
AD9910 Data Sheet SERIAL PROGRAMMING CONTROL INTERFACE—SERIAL I/O The AD9910 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats. The interface allows read/write access to all registers that configure the AD9910. MSB-first or LSB-first transfer formats are supported.
Data Sheet AD9910 I/O_RESET—Input/Output Reset SERIAL I/O TIMING DIAGRAMS I/O_RESET synchronizes the I/O port state machines without affecting the contents of the addressable registers. An active high input on the I/O_RESET pin causes the current communication cycle to abort. After I/O_RESET returns low (Logic 0), another communication cycle can begin, starting with the instruction byte write.
AD9910 Data Sheet REGISTER MAP AND BIT DESCRIPTIONS Table 17.
Data Sheet Register Name (Serial Address) POW— Phase Offset Word (0x08) ASF— Amplitude Scale Factor (0x09) Multichip Sync (0x0A) Digital Ramp Limit (0x0B) Digital Ramp Step Size (0x0C) Digital Ramp Rate (0x0D) Single Tone Profile 0 (0x0E) Bit Range (Internal Address) 15:8 7:0 AD9910 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Phase offset word[15:8] Phase offset word[7:0] 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7
AD9910 Register Name (Serial Address) RAM Profile 0 (0x0E) Data Sheet Bit Range (Internal Address) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Single Tone Profile 1 (0x0F) RAM Profile 1 (0x0F) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Single Tone Profile 2 (0x10) RAM Profile 2 (0x10) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Bit 7 (MSB) Bit 6 RAM Profile 0 waveform end address[1:0] RAM Profile 0 wavefo
Data Sheet Register Name (Serial Address) Single Tone Profile 3 (0x11) RAM Profile 3 (0x11) Bit Range (Internal Address) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 AD9910 Bit 7 (MSB) Bit 6 Open RAM Profile 3 waveform end address[1:0] 23:16 15:8 7:0 Single Tone Profile 4 (0x12) RAM Profile 4 (0x12) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Single Tone Profile 5 (0x13) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 RAM Pr
AD9910 Register Name (Serial Address) RAM Profile 5 (0x13) Data Sheet Bit Range (Internal Address) 63:56 55:48 47:40 39:32 31:24 Bit 7 (MSB) Bit 6 RAM Profile 5 waveform end address[1:0] 23:16 15:8 7:0 Single Tone Profile 6 (0x14) RAM Profile 6 (0x14) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Single Tone Profile 7 (0x15) RAM Profile 7 (0x15) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 RAM Profile 5 waveform start addre
Data Sheet AD9910 REGISTER BIT DESCRIPTIONS The serial I/O port registers span an address range of 0 to 23 (0x00 to 0x16 in hexadecimal notation). This represents a total of 24 registers. However, two of these registers are unused, yielding a total of 22 available registers. The unused registers are Register 5 and Register 6 (0x05 and 0x06, respectively). The number of bytes assigned to the registers varies.
AD9910 Data Sheet Bit(s) 12 Mnemonic Clear digital ramp accumulator 11 Clear phase accumulator 10 Load ARR @ I/O update 9 OSK enable 8 Select auto OSK 7 Digital power-down 6 DAC power-down 5 REFCLK input power-down 4 Auxiliary DAC power-down 3 External power-down control 2 1 Open SDIO input only 0 LSB first Description 0 = normal operation of the DRG accumulator (default). 1 = asynchronous, static reset of the DRG accumulator.
Data Sheet AD9910 Control Function Register 2 (CFR2)—Address 0x01 Four bytes are assigned to this register. Table 19.
AD9910 Data Sheet Bit(s) 6 Mnemonic Data assembler hold last value 5 Sync timing validation disable 4 Parallel data port enable 3:0 FM gain Description Ineffective unless CFR2[4] = 1. 0 = the data assembler of the parallel data port internally forces zeros on the data path and ignores the signals on the D[15:0] and F[1:0] pins while the TxENABLE pin is Logic 0 (default). This implies that the destination of the data at the parallel data port is amplitude when TxENABLE is Logic 0.
Data Sheet AD9910 I/O Update Rate Register—Address 0x04 Four bytes are assigned to this register. This register is effective without the need for an I/O update. Table 22. Bit Descriptions for I/O Update Rate Register Bit(s) 31:0 Mnemonic I/O update rate Description Ineffective unless CFR2[23] = 1. This 32-bit number controls the automatic I/O update rate (see the Automatic I/O Update section for details); default is 0xFFFFFFFF.
AD9910 Data Sheet Multichip Sync Register—Address 0x0A Four bytes are assigned to this register. Table 26.
Data Sheet AD9910 Profile Registers There are eight consecutive serial I/O addresses (Address 0x0E to Address 0x015) dedicated to device profiles. All eight profile registers are either single tone profiles or RAM profiles. RAM profiles are in effect when CFR1[31] = 1. Single tone profiles are in effect when CFR1[31] = 0, CFR2[19] = 0, and CFR2[4] = 0. In normal operation, the active profile register is selected using the external PROFILE[2:0] pins.
AD9910 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 76 100 1 75 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 5.00 SQ 0° MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 51 25 26 BOTTOM VIEW (PINS UP) 51 50 26 0.50 BSC LEAD PITCH VIEW A 25 50 0.27 0.22 0.
Data Sheet AD9910 NOTES Rev.
AD9910 Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06479-0-5/12(D) Rev.
