Datasheet

AD9889B
Rev. A | Page 7 of 12
J
K
A
B
C
D
E
F
G
H
10 8 7 6 3 2 1954
6291-004
BOTTOM VIEW
(Not to Scale)
0
Figure 4. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type
1
Description BGA LFCSP LQFP
D10, D9, C10,
C9, A10, B10,
A9, B9, A8, B8,
A7, B7, A6, B6,
A5, B5, A4, B4,
A3, B3, A2, B2,
A1, B1
39 to 47,
50 to 63, 2
50 to 58, 65 to
78, 2
D[23:0] I
Video Data Input. Digital input in RGB or YCbCr format.
Supports CMOS logic levels from 1.8 V to 3.3 V.
D1 6 6 CLK I
Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
C2 3 3 DE I
Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
C1 4 4 HSYNC I
Horizontal Sync Input. Supports CMOS logic levels from
1.8 V to 3.3 V.
D2 5 5 VSYNC I
Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
J3 18 23 EXT_SWG I
Sets Internal Reference Currents. Place 887 Ω resistor
(1% tolerance) between this pin and ground.
K3 20 25 HPD I
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. Supports 1.8 V to 5.0 V
CMOS logic levels.
E2 7 7 S/PDIF I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is
the audio input from a Sony/Philips digital interface.
Supports CMOS logic levels from 1.8 V to 3.3 V.
E1 8 8 MCLK I
Audio Reference Clock. 128 × N × f
S
with N = 1, 2, 3, or 4.
Set to 128 × sampling frequency (f
S
), 256 × f
S
, 384 × f
S
, or
512 × f
S
. Supports 1.8 V to 3.3 V CMOS logic levels.
F2, F1, G2, G1 9 to 12 9 to 12 I
2
S[3:0] I
I
2
S Audio Data Inputs. These represent the eight channels of
audio (two per input) available through I
2
S. Supports CMOS
logic levels from 1.8 V to 3.3 V.
H2 13 13 SCLK I I
2
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
H1 14 14 LRCLK I
Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
J7
2
26
2
33
2
PD/A0 I
Power-Down Control and I
2
C Address Selection. The I
2
C
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. Supports
1.8 V to 3.3 V CMOS logic levels.
K1, K2 21, 22 27, 28 TxC−/TxC+ O
Differential Clock Output. Differential clock output at pixel
clock rate; supports TMDS logic level.
K10, J10 30, 31 37, 38 Tx2−/Tx2+ O
Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; supports TMDS logic level.