Datasheet

Data Sheet AD9888
Rev. C | Page 5 of 36
AD9888KSZ-100/-140
1
AD9888KSZ-170
Parameter Temp
Te st
Level
Min Typ Max Min Typ Max Unit
DIGITAL INPUTS Full
Input Voltage, High (V
IH
) Full VI 2.5 2.5 V
Input Voltage, Low (V
IL
) Full VI 0.8 0.8 V
Input Current, High (I
IH
) Full IV −1.0 −1.0 μA
Input Current, Low (I
IL
) Full IV +1.0 +1.0 μA
Input Capacitance 25°C V 3 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V
OH
) Full VI V
D
− 0.1 V
D
− 0.1 V
Output Voltage, Low (V
OL
) Full VI 0.1 V
Duty Cycle Full
DATACK, DATACK
Full IV 44 49 55 44 49 55 %
Output Coding Full IV Binary Binary
POWER SUPPLY
Analog Power Supply Voltage (V
D
) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Output Power Supply Voltage (V
DD
) Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V
PLL Power Supply Voltage (P
VD
) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Analog Power Supply Current (I
D
) 25°C 200 215 mA
Output Power Supply Current (I
DD
)
4
25°C 50 55 mA
PLL Power Supply Current (IP
VD
) 25°C 8 9 mA
Total Power Dissipation Full VI 850 1050 920 1150 mW
Power-Down Supply Current Full VI 12 20 12 20 mA
Power-Down Dissipation Full VI 40 66 40 66 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
5
25°C V 500 500 MHz
Transient Response 25°C V 2 2 ns
Overvoltage Recovery Time 25°C V 1.5 1.5 ns
Signal-to-Noise Ratio (SNR)
6
25°C IV 42 45 41 44 dB
Without Harmonics, f
IN
= 40.7 MHz Full V 44 43 dB
Crosstalk Full V 50 50 dBc
THERMAL CHARACTERISTICS
Junction-to-Case Thermal
Resistance (θ
JC
)
V 8.4 8.4 °C/W
Junction-to-Ambient Thermal
Resistance (θ
JA
)
V 35 35 °C/W
1
AD9888JS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz.
2
See Figure 2.
3
The maximum specifications for the AD9888KS-100 and AD9888KS-140 were obtained with VCO range = 10, charge pump current = 100, PLL divider = 1693. The
maximum specifications for the AD9888KS-170 were obtained with VCO range = 11, charge pump current = 100, PLL divider = 2159.
4
DEMUX = 1, DATACK and
DATACK
load = 15 pF, data load = 5 pF.
5
Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, or 75 MHz.
6
Using an external pixel clock.
t
STAH
t
DHO
t
DSU
t
STASU
t
STOSU
SCL
SDA
t
BUFF
t
DAL
t
DAH
02442-025
Figure 2. Serial Port Read/Write Timing