Datasheet

Data Sheet AD9888
Rev. C | Page 35 of 36
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This can easily be accomplished by
keeping traces short and connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside of the AD9888, creating more
digital noise on its power supplies.
DIGITAL INPUTS
The digital inputs on the AD9888 were designed to work with
3.3 V signals, but are tolerant of 5.0 V signals. Therefore, no
extra components are needed when using 5.0 V logic.
Any noise in the HSYNC input trace produces jitter in the
system. Therefore, minimize the trace length, and do not run
any digital or other high frequency trace near it.
VOLTAGE REFERENCE
The voltage reference should be bypassed with a 0.1 μF
capacitor. Place it as close as possible to the REF BYPASS pin.
Make the ground connection as short as possible.