Datasheet

Data Sheet AD9888
Rev. C | Page 33 of 36
SYNC SLICER
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics signals, only those with sync-on-green. The sync signal
is extracted from the green channel in a two-step process. First,
the SOG input is clamped to its negative peak (typically 0.3 V
below the black level). Next, the signal goes to a comparator
with a variable trigger level, nominally 0.15 V above the clamped
level. The “sliced” sync is typically a composite sync signal
containing both HSYNC and VSYNC.
SYNC SEPARATOR
A sync separator extracts the VSYNC signal from a composite sync
signal by using a low-pass filter-like or integrator-like operation.
It works on the idea that the VSYNC signal stays active for a much
longer time than the HSYNC signal. Therefore, the sync separator
rejects any signal shorter than a threshold value, which is some-
where between an HSYNC pulse width and a VSYNC pulse width.
The sync separator on the AD9888 is an 8-bit digital counter
with a 5 MHz clock. It works independently of the polarity of
the composite sync signal. Polarities are determined elsewhere
on the chip. The basic idea is that the counter counts up when
HSYNC pulses are present. Because HSYNC pulses are relatively
short in width, the counter only reaches a value of N before the
pulse ends. It then starts counting down, eventually reaching 0
before the next HSYNC pulse arrives. The specific value of N varies
among video modes, but is always less than 255. For example, with
a 1 μs width HSYNC, the counter reaches only 5 (1 μs/200 ns = 5).
When VSYNC is present on the composite sync, the counter
also counts up. However, because the VSYNC signal is much
longer, the counter reaches a higher number, M. For most video
modes, M is at least 255. Therefore, VSYNC can be detected on
the composite sync signal by detecting when the counter counts
to higher than N. The specific count that triggers detection (T)
can be programmed through the serial register (Address 0x0F).
After VSYNC is detected, there is a similar process to detect when
it becomes inactive. Upon detection, the counter first resets to 0,
and then starts counting up when VSYNC disappears. Similar to
the previous case, the sync separator detects the absence of VSYNC
when the counter reaches the threshold count (T). In this way,
the sync separator rejects noise and/or serration pulses. After
VSYNC is detected to be absent, the counter resets to 0 and begins
the cycle again.