Datasheet

AD9888 Data Sheet
Rev. C | Page 32 of 36
7. Data byte to (base address + 3)
8. Stop signal
Read from One Control Register
1. Start signal
2. Slave address byte (R/
W
bit = low)
3. Base address byte
4. Start signal
5. Slave address byte (R/
W
bit = high)
6. Data byte from base address
7. Stop signal
Read from Four Consecutive Control Registers
1. Start signal
2. Slave address byte (R/
W
bit = low)
3. Base address byte
4. Start signal
5. Slave address byte (R/
W
bit = high)
6. Data byte from base address
7. Data byte from (base address + 1)
8. Data byte from (base address + 2)
9. Data byte from (base address + 3)
10. Stop signal
SYNC PROCESSING
Figure 27 shows the sync processing block diagram, and Table 47
provides information related to serial register controls.
Table 47. Control of the Sync Block Muxes via the
Serial Register
Mux
Number(s)
Serial Bus
Control Bit
Control Bit
State Result
1 and 2 0x0E, Bit 3 0 Pass HSYNC signal
1
Pass sync-on-green
signal
3 0x0F, Bit 5 0 Pass coast signal
1 Pass VSYNC signal
4 0x0E, Bit 0 0 Pass VSYNC signal
1
Pass sync separator
signal
5 0x15, Bit 3 0
Pass Channel 0
inputs
1
Pass Channel 1
inputs
SYNC SLICER
NEGATIVE PEAK
CLAMP
COMP
SYNC
SOGIN0
HSYNC0
PIXEL CLOCK
MUX 1
SYNC SEPARATOR
INTEGRATOR
VSYNC
SOGOUT
HSOUT
VSOUT
MUX 4
1/S
PLL
HSYNC
ACTIVITY
DETECT
AD9888
CLOCK
GENERATOR
COAST
COAST
HSYNC1
SOGIN1
ACTIVITY
DETECT
ACTIVITY
DETECT
POLARITY
DETECT
POLARITY
DETECT
POLARITY
DETECT
MUX 2
MUX 3
MUX 5
MUX 5
VSYNC0
VSYNC1
MUX 5
02442-027
Figure 27. Sync Processing Block Diagram