Datasheet

AD9888 Data Sheet

Rev. C | Page 30 of 36

Address 0x15[2:1]—Analog Bandwidth Control

These bits select the analog bandwidth.

Table 44. Analog Bandwidth Control Settings

Analog Bandwidth Control

Setting Analog Bandwidth

00 75 MHz

01 150 MHz

10 300 MHz

11 (default) 500 MHz

Address 0x15[0]—External Clock Select

This bit determines the source of the pixel clock.

Table 45. External Clock Select Settings

External Clock Select Setting Function

0 (default) Internally generated clock

1 Externally provided clock signal

A Logic 0 enables the internal PLL that generates the pixel clock

from an externally provided HSYNC.

A Logic 1 enables the external CKEXT input pin. In this mode,

the PLL divide ratio (PLLDIV) is ignored. The clock phase adjust